2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "base/trace.hh"
35 #include "cpu/intr_control.hh"
37 #include "dev/pcireg.h"
38 #include "dev/pciconfigall.hh"
39 #include "dev/ide_disk.hh"
40 #include "dev/ide_ctrl.hh"
41 #include "dev/tsunami_cchip.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "mem/bus/dma_interface.hh"
46 #include "dev/tsunami.hh"
47 #include "mem/functional_mem/memory_control.hh"
48 #include "mem/functional_mem/physical_memory.hh"
49 #include "sim/builder.hh"
50 #include "sim/sim_object.hh"
55 // Initialization and destruction
58 IdeController::IdeController(const string
&name
, IntrControl
*ic
,
59 const vector
<IdeDisk
*> &new_disks
,
60 MemoryController
*mmu
, PciConfigAll
*cf
,
61 PciConfigData
*cd
, Tsunami
*t
, uint32_t bus_num
,
62 uint32_t dev_num
, uint32_t func_num
,
63 Bus
*host_bus
, Tick pio_latency
, HierParams
*hier
)
64 : PciDev(name
, mmu
, cf
, cd
, bus_num
, dev_num
, func_num
), tsunami(t
)
66 // put back pointer into Tsunami
67 tsunami
->disk_controller
= this;
69 // initialize the PIO interface addresses
71 pri_cmd_size
= BARSize
[0];
74 pri_ctrl_size
= BARSize
[1];
77 sec_cmd_size
= BARSize
[2];
80 sec_ctrl_size
= BARSize
[3];
82 // initialize the bus master interface (BMI) address to be configured
85 bmi_size
= BARSize
[4];
87 // zero out all of the registers
88 memset(bmi_regs
, 0, sizeof(bmi_regs
));
89 memset(pci_regs
, 0, sizeof(pci_regs
));
91 // setup initial values
92 *(uint32_t *)&pci_regs
[IDETIM
] = 0x80008000; // enable both channels
93 *(uint8_t *)&bmi_regs
[BMIS0
] = 0x60;
94 *(uint8_t *)&bmi_regs
[BMIS1
] = 0x60;
96 // reset all internal variables
99 memset(cmd_in_progress
, 0, sizeof(cmd_in_progress
));
101 // create the PIO and DMA interfaces
103 pioInterface
= newPioInterface(name
, hier
, host_bus
, this,
104 &IdeController::cacheAccess
);
106 dmaInterface
= new DMAInterface
<Bus
>(name
+ ".dma", host_bus
,
108 pioLatency
= pio_latency
* host_bus
->clockRatio
;
111 // setup the disks attached to controller
112 memset(disks
, 0, sizeof(IdeDisk
*) * 4);
114 if (new_disks
.size() > 3)
115 panic("IDE controllers support a maximum of 4 devices attached!\n");
117 for (int i
= 0; i
< new_disks
.size(); i
++) {
118 disks
[i
] = new_disks
[i
];
119 disks
[i
]->setController(this, dmaInterface
);
123 IdeController::~IdeController()
125 for (int i
= 0; i
< 4; i
++)
135 IdeController::parseAddr(const Addr
&addr
, Addr
&offset
, bool &primary
,
140 if (addr
>= pri_cmd_addr
&& addr
< (pri_cmd_addr
+ pri_cmd_size
)) {
141 offset
-= pri_cmd_addr
;
142 type
= COMMAND_BLOCK
;
144 } else if (addr
>= pri_ctrl_addr
&&
145 addr
< (pri_ctrl_addr
+ pri_ctrl_size
)) {
146 offset
-= pri_ctrl_addr
;
147 type
= CONTROL_BLOCK
;
149 } else if (addr
>= sec_cmd_addr
&&
150 addr
< (sec_cmd_addr
+ sec_cmd_size
)) {
151 offset
-= sec_cmd_addr
;
152 type
= COMMAND_BLOCK
;
154 } else if (addr
>= sec_ctrl_addr
&&
155 addr
< (sec_ctrl_addr
+ sec_ctrl_size
)) {
156 offset
-= sec_ctrl_addr
;
157 type
= CONTROL_BLOCK
;
159 } else if (addr
>= bmi_addr
&& addr
< (bmi_addr
+ bmi_size
)) {
162 primary
= (offset
< BMIC1
) ? true : false;
164 panic("IDE controller access to invalid address: %#x\n", addr
);
169 IdeController::getDisk(bool primary
)
172 uint8_t *devBit
= &dev
[0];
181 assert(*devBit
== 0 || *devBit
== 1);
187 IdeController::getDisk(IdeDisk
*diskPtr
)
189 for (int i
= 0; i
< 4; i
++) {
190 if ((long)diskPtr
== (long)disks
[i
])
197 IdeController::isDiskSelected(IdeDisk
*diskPtr
)
199 for (int i
= 0; i
< 4; i
++) {
200 if ((long)diskPtr
== (long)disks
[i
]) {
201 // is disk is on primary or secondary channel
203 // is disk the master or slave
206 return (dev
[channel
] == devID
);
209 panic("Unable to find disk by pointer!!\n");
213 // Command completion
217 IdeController::setDmaComplete(IdeDisk
*disk
)
219 int diskNum
= getDisk(disk
);
222 panic("Unable to find disk based on pointer %#x\n", disk
);
225 // clear the start/stop bit in the command register
226 bmi_regs
[BMIC0
] &= ~SSBM
;
227 // clear the bus master active bit in the status register
228 bmi_regs
[BMIS0
] &= ~BMIDEA
;
229 // set the interrupt bit
230 bmi_regs
[BMIS0
] |= IDEINTS
;
232 // clear the start/stop bit in the command register
233 bmi_regs
[BMIC1
] &= ~SSBM
;
234 // clear the bus master active bit in the status register
235 bmi_regs
[BMIS1
] &= ~BMIDEA
;
236 // set the interrupt bit
237 bmi_regs
[BMIS1
] |= IDEINTS
;
242 // Interrupt handling
246 IdeController::intrPost()
248 tsunami
->cchip
->postDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
252 IdeController::intrClear()
254 tsunami
->cchip
->clearDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
258 // Bus timing and bus access functions
262 IdeController::cacheAccess(MemReqPtr
&req
)
264 // @todo Add more accurate timing to cache access
265 return curTick
+ pioLatency
;
269 // Read and write handling
273 IdeController::ReadConfig(int offset
, int size
, uint8_t *data
)
277 Addr origOffset
= offset
;
280 if (offset
< PCI_DEVICE_SPECIFIC
) {
281 PciDev::ReadConfig(offset
, size
, data
);
283 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
284 offset
-= PCI_IDE_TIMING
;
287 if ((offset
+ size
) > (IDETIM
+ 4))
288 panic("PCI read of IDETIM with invalid size\n");
289 } else if (offset
== PCI_SLAVE_TIMING
) {
290 offset
-= PCI_SLAVE_TIMING
;
293 if ((offset
+ size
) > (SIDETIM
+ 1))
294 panic("PCI read of SIDETIM with invalid size\n");
295 } else if (offset
== PCI_UDMA33_CTRL
) {
296 offset
-= PCI_UDMA33_CTRL
;
299 if ((offset
+ size
) > (UDMACTL
+ 1))
300 panic("PCI read of UDMACTL with invalid size\n");
301 } else if (offset
>= PCI_UDMA33_TIMING
&&
302 offset
< (PCI_UDMA33_TIMING
+ 2)) {
303 offset
-= PCI_UDMA33_TIMING
;
306 if ((offset
+ size
) > (UDMATIM
+ 2))
307 panic("PCI read of UDMATIM with invalid size\n");
309 panic("PCI read of unimplemented register: %x\n", offset
);
312 memcpy((void *)data
, (void *)&pci_regs
[offset
], size
);
315 DPRINTF(IdeCtrl
, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
316 origOffset
, offset
, size
, *(uint32_t *)data
);
320 IdeController::WriteConfig(int offset
, int size
, uint32_t data
)
322 DPRINTF(IdeCtrl
, "IDE PCI write offset: %#x size: %#x data: %#x\n",
325 // do standard write stuff if in standard PCI space
326 if (offset
< PCI_DEVICE_SPECIFIC
) {
327 PciDev::WriteConfig(offset
, size
, data
);
329 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
330 offset
-= PCI_IDE_TIMING
;
333 if ((offset
+ size
) > (IDETIM
+ 4))
334 panic("PCI write to IDETIM with invalid size\n");
335 } else if (offset
== PCI_SLAVE_TIMING
) {
336 offset
-= PCI_SLAVE_TIMING
;
339 if ((offset
+ size
) > (SIDETIM
+ 1))
340 panic("PCI write to SIDETIM with invalid size\n");
341 } else if (offset
== PCI_UDMA33_CTRL
) {
342 offset
-= PCI_UDMA33_CTRL
;
345 if ((offset
+ size
) > (UDMACTL
+ 1))
346 panic("PCI write to UDMACTL with invalid size\n");
347 } else if (offset
>= PCI_UDMA33_TIMING
&&
348 offset
< (PCI_UDMA33_TIMING
+ 2)) {
349 offset
-= PCI_UDMA33_TIMING
;
352 if ((offset
+ size
) > (UDMATIM
+ 2))
353 panic("PCI write to UDMATIM with invalid size\n");
355 panic("PCI write to unimplemented register: %x\n", offset
);
358 memcpy((void *)&pci_regs
[offset
], (void *)&data
, size
);
361 // Catch the writes to specific PCI registers that have side affects
362 // (like updating the PIO ranges)
365 if (config
.data
[offset
] & PCI_CMD_IOSE
)
370 if (config
.data
[offset
] & PCI_CMD_BME
)
376 case PCI0_BASE_ADDR0
:
377 if (BARAddrs
[0] != 0) {
378 pri_cmd_addr
= BARAddrs
[0];
380 pioInterface
->addAddrRange(pri_cmd_addr
,
381 pri_cmd_addr
+ pri_cmd_size
- 1);
383 pri_cmd_addr
&= PA_UNCACHED_MASK
;
387 case PCI0_BASE_ADDR1
:
388 if (BARAddrs
[1] != 0) {
389 pri_ctrl_addr
= BARAddrs
[1];
391 pioInterface
->addAddrRange(pri_ctrl_addr
,
392 pri_ctrl_addr
+ pri_ctrl_size
- 1);
394 pri_ctrl_addr
&= PA_UNCACHED_MASK
;
398 case PCI0_BASE_ADDR2
:
399 if (BARAddrs
[2] != 0) {
400 sec_cmd_addr
= BARAddrs
[2];
402 pioInterface
->addAddrRange(sec_cmd_addr
,
403 sec_cmd_addr
+ sec_cmd_size
- 1);
405 sec_cmd_addr
&= PA_UNCACHED_MASK
;
409 case PCI0_BASE_ADDR3
:
410 if (BARAddrs
[3] != 0) {
411 sec_ctrl_addr
= BARAddrs
[3];
413 pioInterface
->addAddrRange(sec_ctrl_addr
,
414 sec_ctrl_addr
+ sec_ctrl_size
- 1);
416 sec_ctrl_addr
&= PA_UNCACHED_MASK
;
420 case PCI0_BASE_ADDR4
:
421 if (BARAddrs
[4] != 0) {
422 bmi_addr
= BARAddrs
[4];
424 pioInterface
->addAddrRange(bmi_addr
, bmi_addr
+ bmi_size
- 1);
426 bmi_addr
&= PA_UNCACHED_MASK
;
433 IdeController::read(MemReqPtr
&req
, uint8_t *data
)
442 parseAddr(req
->paddr
, offset
, primary
, type
);
443 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
444 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
449 // sanity check the size (allows byte, word, or dword access)
450 if (req
->size
!= sizeof(uint8_t) && req
->size
!= sizeof(uint16_t) &&
451 req
->size
!= sizeof(uint32_t))
452 panic("IDE controller read of invalid size: %#x\n", req
->size
);
454 if (type
!= BMI_BLOCK
) {
455 assert(req
->size
!= sizeof(uint32_t));
457 disk
= getDisk(primary
);
459 disks
[disk
]->read(offset
, byte
, cmdBlk
, data
);
461 memcpy((void *)data
, &bmi_regs
[offset
], req
->size
);
464 DPRINTF(IdeCtrl
, "IDE read from offset: %#x size: %#x data: %#x\n",
465 offset
, req
->size
, *(uint32_t *)data
);
471 IdeController::write(MemReqPtr
&req
, const uint8_t *data
)
480 parseAddr(req
->paddr
, offset
, primary
, type
);
481 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
482 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
484 DPRINTF(IdeCtrl
, "IDE write from offset: %#x size: %#x data: %#x\n",
485 offset
, req
->size
, *(uint32_t *)data
);
487 uint8_t oldVal
, newVal
;
492 if (type
== BMI_BLOCK
&& !bm_enabled
)
495 if (type
!= BMI_BLOCK
) {
496 // shadow the dev bit
497 if (type
== COMMAND_BLOCK
&& offset
== IDE_SELECT_OFFSET
) {
498 uint8_t *devBit
= (primary
? &dev
[0] : &dev
[1]);
499 *devBit
= ((*data
& IDE_SELECT_DEV_BIT
) ? 1 : 0);
502 assert(req
->size
!= sizeof(uint32_t));
504 disk
= getDisk(primary
);
506 disks
[disk
]->write(offset
, byte
, cmdBlk
, data
);
509 // Bus master IDE command register
512 if (req
->size
!= sizeof(uint8_t))
513 panic("Invalid BMIC write size: %x\n", req
->size
);
515 // select the current disk based on DEV bit
516 disk
= getDisk(primary
);
518 oldVal
= bmi_regs
[offset
];
521 // if a DMA transfer is in progress, R/W control cannot change
523 if ((oldVal
& RWCON
) ^ (newVal
& RWCON
)) {
524 (oldVal
& RWCON
) ? newVal
|= RWCON
: newVal
&= ~RWCON
;
528 // see if the start/stop bit is being changed
529 if ((oldVal
& SSBM
) ^ (newVal
& SSBM
)) {
531 // stopping DMA transfer
532 DPRINTF(IdeCtrl
, "Stopping DMA transfer\n");
534 // clear the BMIDEA bit
535 bmi_regs
[offset
+ 0x2] &= ~BMIDEA
;
537 if (disks
[disk
] == NULL
)
538 panic("DMA stop for disk %d which does not exist\n",
541 // inform the disk of the DMA transfer abort
542 disks
[disk
]->abortDma();
544 // starting DMA transfer
545 DPRINTF(IdeCtrl
, "Starting DMA transfer\n");
547 // set the BMIDEA bit
548 bmi_regs
[offset
+ 0x2] |= BMIDEA
;
550 if (disks
[disk
] == NULL
)
551 panic("DMA start for disk %d which does not exist\n",
554 // inform the disk of the DMA transfer start
556 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP0
]);
558 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP1
]);
562 // update the register value
563 bmi_regs
[offset
] = newVal
;
566 // Bus master IDE status register
569 if (req
->size
!= sizeof(uint8_t))
570 panic("Invalid BMIS write size: %x\n", req
->size
);
572 oldVal
= bmi_regs
[offset
];
575 // the BMIDEA bit is RO
576 newVal
|= (oldVal
& BMIDEA
);
578 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
579 if ((oldVal
& IDEINTS
) && (newVal
& IDEINTS
))
580 newVal
&= ~IDEINTS
; // clear the interrupt?
582 (oldVal
& IDEINTS
) ? newVal
|= IDEINTS
: newVal
&= ~IDEINTS
;
584 if ((oldVal
& IDEDMAE
) && (newVal
& IDEDMAE
))
587 (oldVal
& IDEDMAE
) ? newVal
|= IDEDMAE
: newVal
&= ~IDEDMAE
;
589 bmi_regs
[offset
] = newVal
;
592 // Bus master IDE descriptor table pointer register
595 if (req
->size
!= sizeof(uint32_t))
596 panic("Invalid BMIDTP write size: %x\n", req
->size
);
598 *(uint32_t *)&bmi_regs
[offset
] = *(uint32_t *)data
& ~0x3;
602 if (req
->size
!= sizeof(uint8_t) &&
603 req
->size
!= sizeof(uint16_t) &&
604 req
->size
!= sizeof(uint32_t))
605 panic("IDE controller write of invalid write size: %x\n",
608 // do a default copy of data into the registers
609 memcpy((void *)&bmi_regs
[offset
], data
, req
->size
);
621 IdeController::serialize(std::ostream
&os
)
623 // Serialize the PciDev base class
624 PciDev::serialize(os
);
626 // Serialize register addresses and sizes
627 SERIALIZE_SCALAR(pri_cmd_addr
);
628 SERIALIZE_SCALAR(pri_cmd_size
);
629 SERIALIZE_SCALAR(pri_ctrl_addr
);
630 SERIALIZE_SCALAR(pri_ctrl_size
);
631 SERIALIZE_SCALAR(sec_cmd_addr
);
632 SERIALIZE_SCALAR(sec_cmd_size
);
633 SERIALIZE_SCALAR(sec_ctrl_addr
);
634 SERIALIZE_SCALAR(sec_ctrl_size
);
635 SERIALIZE_SCALAR(bmi_addr
);
636 SERIALIZE_SCALAR(bmi_size
);
638 // Serialize registers
639 SERIALIZE_ARRAY(bmi_regs
, 16);
640 SERIALIZE_ARRAY(dev
, 2);
641 SERIALIZE_ARRAY(pci_regs
, 8);
643 // Serialize internal state
644 SERIALIZE_SCALAR(io_enabled
);
645 SERIALIZE_SCALAR(bm_enabled
);
646 SERIALIZE_ARRAY(cmd_in_progress
, 4);
650 IdeController::unserialize(Checkpoint
*cp
, const std::string
§ion
)
652 // Unserialize the PciDev base class
653 PciDev::unserialize(cp
, section
);
655 // Unserialize register addresses and sizes
656 UNSERIALIZE_SCALAR(pri_cmd_addr
);
657 UNSERIALIZE_SCALAR(pri_cmd_size
);
658 UNSERIALIZE_SCALAR(pri_ctrl_addr
);
659 UNSERIALIZE_SCALAR(pri_ctrl_size
);
660 UNSERIALIZE_SCALAR(sec_cmd_addr
);
661 UNSERIALIZE_SCALAR(sec_cmd_size
);
662 UNSERIALIZE_SCALAR(sec_ctrl_addr
);
663 UNSERIALIZE_SCALAR(sec_ctrl_size
);
664 UNSERIALIZE_SCALAR(bmi_addr
);
665 UNSERIALIZE_SCALAR(bmi_size
);
667 // Unserialize registers
668 UNSERIALIZE_ARRAY(bmi_regs
, 16);
669 UNSERIALIZE_ARRAY(dev
, 2);
670 UNSERIALIZE_ARRAY(pci_regs
, 8);
672 // Unserialize internal state
673 UNSERIALIZE_SCALAR(io_enabled
);
674 UNSERIALIZE_SCALAR(bm_enabled
);
675 UNSERIALIZE_ARRAY(cmd_in_progress
, 4);
678 pioInterface
->addAddrRange(pri_cmd_addr
, pri_cmd_addr
+
680 pioInterface
->addAddrRange(pri_ctrl_addr
, pri_ctrl_addr
+
682 pioInterface
->addAddrRange(sec_cmd_addr
, sec_cmd_addr
+
684 pioInterface
->addAddrRange(sec_ctrl_addr
, sec_ctrl_addr
+
686 pioInterface
->addAddrRange(bmi_addr
, bmi_addr
+ bmi_size
- 1);
690 #ifndef DOXYGEN_SHOULD_SKIP_THIS
692 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
694 SimObjectParam
<IntrControl
*> intr_ctrl
;
695 SimObjectVectorParam
<IdeDisk
*> disks
;
696 SimObjectParam
<MemoryController
*> mmu
;
697 SimObjectParam
<PciConfigAll
*> configspace
;
698 SimObjectParam
<PciConfigData
*> configdata
;
699 SimObjectParam
<Tsunami
*> tsunami
;
700 Param
<uint32_t> pci_bus
;
701 Param
<uint32_t> pci_dev
;
702 Param
<uint32_t> pci_func
;
703 SimObjectParam
<Bus
*> io_bus
;
704 Param
<Tick
> pio_latency
;
705 SimObjectParam
<HierParams
*> hier
;
707 END_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
709 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController
)
711 INIT_PARAM(intr_ctrl
, "Interrupt Controller"),
712 INIT_PARAM(disks
, "IDE disks attached to this controller"),
713 INIT_PARAM(mmu
, "Memory controller"),
714 INIT_PARAM(configspace
, "PCI Configspace"),
715 INIT_PARAM(configdata
, "PCI Config data"),
716 INIT_PARAM(tsunami
, "Tsunami chipset pointer"),
717 INIT_PARAM(pci_bus
, "PCI bus ID"),
718 INIT_PARAM(pci_dev
, "PCI device number"),
719 INIT_PARAM(pci_func
, "PCI function code"),
720 INIT_PARAM_DFLT(io_bus
, "Host bus to attach to", NULL
),
721 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
722 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
724 END_INIT_SIM_OBJECT_PARAMS(IdeController
)
726 CREATE_SIM_OBJECT(IdeController
)
728 return new IdeController(getInstanceName(), intr_ctrl
, disks
, mmu
,
729 configspace
, configdata
, tsunami
, pci_bus
,
730 pci_dev
, pci_func
, io_bus
, pio_latency
, hier
);
733 REGISTER_SIM_OBJECT("IdeController", IdeController
)
735 #endif //DOXYGEN_SHOULD_SKIP_THIS