dev/ide_ctrl.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstddef>
  30 #include <cstdlib>
  31 #include <string>
  32 #include <vector>
  33
  34 #include "base/trace.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/dma.hh"
  37 #include "dev/pcireg.h"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/ide_disk.hh"
  40 #include "dev/ide_ctrl.hh"
  41 #include "dev/tsunami_cchip.hh"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/bus/dma_interface.hh"
  46 #include "dev/tsunami.hh"
  47 #include "mem/functional_mem/memory_control.hh"
  48 #include "mem/functional_mem/physical_memory.hh"
  49 #include "sim/builder.hh"
  50 #include "sim/sim_object.hh"
  51
  52 using namespace std;
  53
  54 ////
  55 // Initialization and destruction
  56 ////
  57
  58 IdeController::IdeController(const string &name, IntrControl *ic,
  59                              const vector<IdeDisk *> &new_disks,
  60                              MemoryController *mmu, PciConfigAll *cf,
  61                              PciConfigData *cd, Tsunami *t, uint32_t bus_num,
  62                              uint32_t dev_num, uint32_t func_num,
  63                              Bus *host_bus, HierParams *hier)
  64     : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
  65 {
  66     // put back pointer into Tsunami
  67     tsunami->disk_controller = this;
  68
  69     // initialize the PIO interface addresses
  70     pri_cmd_addr = 0;
  71     pri_cmd_size = BARSize[0];
  72
  73     pri_ctrl_addr = 0;
  74     pri_ctrl_size = BARSize[1];
  75
  76     sec_cmd_addr = 0;
  77     sec_cmd_size = BARSize[2];
  78
  79     sec_ctrl_addr = 0;
  80     sec_ctrl_size = BARSize[3];
  81
  82     // initialize the bus master interface (BMI) address to be configured
  83     // via PCI
  84     bmi_addr = 0;
  85     bmi_size = BARSize[4];
  86
  87     // zero out all of the registers
  88     memset(bmi_regs, 0, sizeof(bmi_regs));
  89     memset(pci_regs, 0, sizeof(pci_regs));
  90
  91     // setup initial values
  92     *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels
  93     *(uint8_t *)&bmi_regs[BMIS0] = 0x60;
  94     *(uint8_t *)&bmi_regs[BMIS1] = 0x60;
  95
  96     // reset all internal variables
  97     io_enabled = false;
  98     bm_enabled = false;
  99     memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
 100
 101     // create the PIO and DMA interfaces
 102     if (host_bus) {
 103         pioInterface = newPioInterface(name, hier, host_bus, this,
 104                                        &IdeController::cacheAccess);
 105
 106         dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus,
 107                                              host_bus, 1);
 108     }
 109
 110     // setup the disks attached to controller
 111     memset(disks, 0, sizeof(IdeDisk *) * 4);
 112
 113     if (new_disks.size() > 3)
 114         panic("IDE controllers support a maximum of 4 devices attached!\n");
 115
 116     for (int i = 0; i < new_disks.size(); i++) {
 117         disks[i] = new_disks[i];
 118         disks[i]->setController(this, dmaInterface);
 119     }
 120 }
 121
 122 IdeController::~IdeController()
 123 {
 124     for (int i = 0; i < 4; i++)
 125         if (disks[i])
 126             delete disks[i];
 127 }
 128
 129 ////
 130 // Command completion
 131 ////
 132
 133 void
 134 IdeController::setDmaComplete(IdeDisk *disk)
 135 {
 136     int diskNum = getDisk(disk);
 137
 138     if (diskNum < 0)
 139         panic("Unable to find disk based on pointer %#x\n", disk);
 140
 141     if (diskNum < 2) {
 142         // clear the start/stop bit in the command register
 143         bmi_regs[BMIC0] &= ~SSBM;
 144         // clear the bus master active bit in the status register
 145         bmi_regs[BMIS0] &= ~BMIDEA;
 146         // set the interrupt bit
 147         bmi_regs[BMIS0] |= IDEINTS;
 148     } else {
 149         // clear the start/stop bit in the command register
 150         bmi_regs[BMIC1] &= ~SSBM;
 151         // clear the bus master active bit in the status register
 152         bmi_regs[BMIS1] &= ~BMIDEA;
 153         // set the interrupt bit
 154         bmi_regs[BMIS1] |= IDEINTS;
 155     }
 156 }
 157
 158 ////
 159 // Interrupt handling
 160 ////
 161
 162 void
 163 IdeController::intrPost()
 164 {
 165     tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
 166 }
 167
 168 void
 169 IdeController::intrClear()
 170 {
 171     tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
 172 }
 173
 174 ////
 175 // Bus timing and bus access functions
 176 ////
 177
 178 Tick
 179 IdeController::cacheAccess(MemReqPtr &req)
 180 {
 181     // @todo Add more accurate timing to cache access
 182     return curTick + 1000;
 183 }
 184
 185 ////
 186 // Read and write handling
 187 ////
 188
 189 void
 190 IdeController::ReadConfig(int offset, int size, uint8_t *data)
 191 {
 192     Addr origOffset = offset;
 193
 194     if (offset < PCI_DEVICE_SPECIFIC) {
 195         PciDev::ReadConfig(offset, size, data);
 196     } else {
 197         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 198             offset -= PCI_IDE_TIMING;
 199             offset += IDETIM;
 200
 201             if ((offset + size) > (IDETIM + 4))
 202                 panic("PCI read of IDETIM with invalid size\n");
 203         } else if (offset == PCI_SLAVE_TIMING) {
 204             offset -= PCI_SLAVE_TIMING;
 205             offset += SIDETIM;
 206
 207             if ((offset + size) > (SIDETIM + 1))
 208                 panic("PCI read of SIDETIM with invalid size\n");
 209         } else if (offset == PCI_UDMA33_CTRL) {
 210             offset -= PCI_UDMA33_CTRL;
 211             offset += UDMACTL;
 212
 213             if ((offset + size) > (UDMACTL + 1))
 214                 panic("PCI read of UDMACTL with invalid size\n");
 215         } else if (offset >= PCI_UDMA33_TIMING &&
 216                    offset < (PCI_UDMA33_TIMING + 2)) {
 217             offset -= PCI_UDMA33_TIMING;
 218             offset += UDMATIM;
 219
 220             if ((offset + size) > (UDMATIM + 2))
 221                 panic("PCI read of UDMATIM with invalid size\n");
 222         } else {
 223             panic("PCI read of unimplemented register: %x\n", offset);
 224         }
 225
 226         memcpy((void *)data, (void *)&pci_regs[offset], size);
 227     }
 228
 229     DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
 230                 origOffset, offset, size, *(uint32_t *)data);
 231 }
 232
 233 void
 234 IdeController::WriteConfig(int offset, int size, uint32_t data)
 235 {
 236     DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n",
 237             offset, size, data);
 238
 239     // do standard write stuff if in standard PCI space
 240     if (offset < PCI_DEVICE_SPECIFIC) {
 241         PciDev::WriteConfig(offset, size, data);
 242     } else {
 243         if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) {
 244             offset -= PCI_IDE_TIMING;
 245             offset += IDETIM;
 246
 247             if ((offset + size) > (IDETIM + 4))
 248                 panic("PCI write to IDETIM with invalid size\n");
 249         } else if (offset == PCI_SLAVE_TIMING) {
 250             offset -= PCI_SLAVE_TIMING;
 251             offset += SIDETIM;
 252
 253             if ((offset + size) > (SIDETIM + 1))
 254                 panic("PCI write to SIDETIM with invalid size\n");
 255         } else if (offset == PCI_UDMA33_CTRL) {
 256             offset -= PCI_UDMA33_CTRL;
 257             offset += UDMACTL;
 258
 259             if ((offset + size) > (UDMACTL + 1))
 260                 panic("PCI write to UDMACTL with invalid size\n");
 261         } else if (offset >= PCI_UDMA33_TIMING &&
 262                    offset < (PCI_UDMA33_TIMING + 2)) {
 263             offset -= PCI_UDMA33_TIMING;
 264             offset += UDMATIM;
 265
 266             if ((offset + size) > (UDMATIM + 2))
 267                 panic("PCI write to UDMATIM with invalid size\n");
 268         } else {
 269             panic("PCI write to unimplemented register: %x\n", offset);
 270         }
 271
 272         memcpy((void *)&pci_regs[offset], (void *)&data, size);
 273     }
 274
 275     if (offset == PCI_COMMAND) {
 276         if (config.data[offset] & IOSE)
 277             io_enabled = true;
 278         else
 279             io_enabled = false;
 280
 281         if (config.data[offset] & BME)
 282             bm_enabled = true;
 283         else
 284             bm_enabled = false;
 285
 286     } else if (data != 0xffffffff) {
 287         switch (offset) {
 288           case PCI0_BASE_ADDR0:
 289             pri_cmd_addr = BARAddrs[0];
 290             if (pioInterface)
 291                 pioInterface->addAddrRange(pri_cmd_addr,
 292                                            pri_cmd_addr + pri_cmd_size - 1);
 293
 294             pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
 295             break;
 296
 297           case PCI0_BASE_ADDR1:
 298             pri_ctrl_addr = BARAddrs[1];
 299             if (pioInterface)
 300                 pioInterface->addAddrRange(pri_ctrl_addr,
 301                                            pri_ctrl_addr + pri_ctrl_size - 1);
 302
 303             pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
 304             break;
 305
 306           case PCI0_BASE_ADDR2:
 307             sec_cmd_addr = BARAddrs[2];
 308             if (pioInterface)
 309                 pioInterface->addAddrRange(sec_cmd_addr,
 310                                            sec_cmd_addr + sec_cmd_size - 1);
 311
 312             sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
 313             break;
 314
 315           case PCI0_BASE_ADDR3:
 316             sec_ctrl_addr = BARAddrs[3];
 317             if (pioInterface)
 318                 pioInterface->addAddrRange(sec_ctrl_addr,
 319                                            sec_ctrl_addr + sec_ctrl_size - 1);
 320
 321             sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
 322             break;
 323
 324           case PCI0_BASE_ADDR4:
 325             bmi_addr = BARAddrs[4];
 326             if (pioInterface)
 327                 pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1);
 328
 329             bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK);
 330             break;
 331         }
 332     }
 333 }
 334
 335 Fault
 336 IdeController::read(MemReqPtr &req, uint8_t *data)
 337 {
 338     Addr offset;
 339     bool primary;
 340     bool byte;
 341     bool cmdBlk;
 342     RegType_t type;
 343     int disk;
 344
 345     parseAddr(req->paddr, offset, primary, type);
 346     byte = (req->size == sizeof(uint8_t)) ? true : false;
 347     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 348
 349     if (!io_enabled)
 350         return No_Fault;
 351
 352     // sanity check the size (allows byte, word, or dword access)
 353     if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) &&
 354         req->size != sizeof(uint32_t))
 355         panic("IDE controller read of invalid size: %#x\n", req->size);
 356
 357     if (type != BMI_BLOCK) {
 358         assert(req->size != sizeof(uint32_t));
 359
 360         disk = getDisk(primary);
 361         if (disks[disk])
 362             disks[disk]->read(offset, byte, cmdBlk, data);
 363     } else {
 364         memcpy((void *)data, &bmi_regs[offset], req->size);
 365     }
 366
 367     DPRINTF(IdeCtrl, "IDE read from offset: %#x size: %#x data: %#x\n",
 368             offset, req->size, *(uint32_t *)data);
 369
 370     return No_Fault;
 371 }
 372
 373 Fault
 374 IdeController::write(MemReqPtr &req, const uint8_t *data)
 375 {
 376     Addr offset;
 377     bool primary;
 378     bool byte;
 379     bool cmdBlk;
 380     RegType_t type;
 381     int disk;
 382
 383     parseAddr(req->paddr, offset, primary, type);
 384     byte = (req->size == sizeof(uint8_t)) ? true : false;
 385     cmdBlk = (type == COMMAND_BLOCK) ? true : false;
 386
 387     DPRINTF(IdeCtrl, "IDE write from offset: %#x size: %#x data: %#x\n",
 388             offset, req->size, *(uint32_t *)data);
 389
 390     uint8_t oldVal, newVal;
 391
 392     if (!io_enabled)
 393         return No_Fault;
 394
 395     if (type == BMI_BLOCK && !bm_enabled)
 396         return No_Fault;
 397
 398     if (type != BMI_BLOCK) {
 399         // shadow the dev bit
 400         if (type == COMMAND_BLOCK && offset == IDE_SELECT_OFFSET) {
 401             uint8_t *devBit = (primary ? &dev[0] : &dev[1]);
 402             *devBit = ((*data & IDE_SELECT_DEV_BIT) ? 1 : 0);
 403         }
 404
 405         assert(req->size != sizeof(uint32_t));
 406
 407         disk = getDisk(primary);
 408         if (disks[disk])
 409             disks[disk]->write(offset, byte, cmdBlk, data);
 410     } else {
 411         switch (offset) {
 412             // Bus master IDE command register
 413           case BMIC1:
 414           case BMIC0:
 415             if (req->size != sizeof(uint8_t))
 416                 panic("Invalid BMIC write size: %x\n", req->size);
 417
 418             // select the current disk based on DEV bit
 419             disk = getDisk(primary);
 420
 421             oldVal = bmi_regs[offset];
 422             newVal = *data;
 423
 424             // if a DMA transfer is in progress, R/W control cannot change
 425             if (oldVal & SSBM) {
 426                 if ((oldVal & RWCON) ^ (newVal & RWCON)) {
 427                     (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON;
 428                 }
 429             }
 430
 431             // see if the start/stop bit is being changed
 432             if ((oldVal & SSBM) ^ (newVal & SSBM)) {
 433                 if (oldVal & SSBM) {
 434                     // stopping DMA transfer
 435                     DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
 436
 437                     // clear the BMIDEA bit
 438                     bmi_regs[offset + 0x2] &= ~BMIDEA;
 439
 440                     if (disks[disk] == NULL)
 441                         panic("DMA stop for disk %d which does not exist\n",
 442                               disk);
 443
 444                     // inform the disk of the DMA transfer abort
 445                     disks[disk]->abortDma();
 446                 } else {
 447                     // starting DMA transfer
 448                     DPRINTF(IdeCtrl, "Starting DMA transfer\n");
 449
 450                     // set the BMIDEA bit
 451                     bmi_regs[offset + 0x2] |= BMIDEA;
 452
 453                     if (disks[disk] == NULL)
 454                         panic("DMA start for disk %d which does not exist\n",
 455                               disk);
 456
 457                     // inform the disk of the DMA transfer start
 458                     if (primary)
 459                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP0]);
 460                     else
 461                         disks[disk]->startDma(*(uint32_t *)&bmi_regs[BMIDTP1]);
 462                 }
 463             }
 464
 465             // update the register value
 466             bmi_regs[offset] = newVal;
 467             break;
 468
 469             // Bus master IDE status register
 470           case BMIS0:
 471           case BMIS1:
 472             if (req->size != sizeof(uint8_t))
 473                 panic("Invalid BMIS write size: %x\n", req->size);
 474
 475             oldVal = bmi_regs[offset];
 476             newVal = *data;
 477
 478             // the BMIDEA bit is RO
 479             newVal |= (oldVal & BMIDEA);
 480
 481             // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
 482             if ((oldVal & IDEINTS) && (newVal & IDEINTS))
 483                 newVal &= ~IDEINTS; // clear the interrupt?
 484             else
 485                 (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS;
 486
 487             if ((oldVal & IDEDMAE) && (newVal & IDEDMAE))
 488                 newVal &= ~IDEDMAE;
 489             else
 490                 (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE;
 491
 492             bmi_regs[offset] = newVal;
 493             break;
 494
 495             // Bus master IDE descriptor table pointer register
 496           case BMIDTP0:
 497           case BMIDTP1:
 498             if (req->size != sizeof(uint32_t))
 499                 panic("Invalid BMIDTP write size: %x\n", req->size);
 500
 501             *(uint32_t *)&bmi_regs[offset] = *(uint32_t *)data & ~0x3;
 502             break;
 503
 504           default:
 505             if (req->size != sizeof(uint8_t) &&
 506                 req->size != sizeof(uint16_t) &&
 507                 req->size != sizeof(uint32_t))
 508                 panic("IDE controller write of invalid write size: %x\n",
 509                       req->size);
 510
 511             // do a default copy of data into the registers
 512             memcpy((void *)&bmi_regs[offset], data, req->size);
 513         }
 514     }
 515
 516     return No_Fault;
 517 }
 518
 519 ////
 520 // Serialization
 521 ////
 522
 523 void
 524 IdeController::serialize(std::ostream &os)
 525 {
 526 }
 527
 528 void
 529 IdeController::unserialize(Checkpoint *cp, const std::string &section)
 530 {
 531 }
 532
 533 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 534
 535 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 536
 537     SimObjectParam<IntrControl *> intr_ctrl;
 538     SimObjectVectorParam<IdeDisk *> disks;
 539     SimObjectParam<MemoryController *> mmu;
 540     SimObjectParam<PciConfigAll *> configspace;
 541     SimObjectParam<PciConfigData *> configdata;
 542     SimObjectParam<Tsunami *> tsunami;
 543     Param<uint32_t> pci_bus;
 544     Param<uint32_t> pci_dev;
 545     Param<uint32_t> pci_func;
 546     SimObjectParam<Bus *> host_bus;
 547     SimObjectParam<HierParams *> hier;
 548
 549 END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
 550
 551 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
 552
 553     INIT_PARAM(intr_ctrl, "Interrupt Controller"),
 554     INIT_PARAM(disks, "IDE disks attached to this controller"),
 555     INIT_PARAM(mmu, "Memory controller"),
 556     INIT_PARAM(configspace, "PCI Configspace"),
 557     INIT_PARAM(configdata, "PCI Config data"),
 558     INIT_PARAM(tsunami, "Tsunami chipset pointer"),
 559     INIT_PARAM(pci_bus, "PCI bus ID"),
 560     INIT_PARAM(pci_dev, "PCI device number"),
 561     INIT_PARAM(pci_func, "PCI function code"),
 562     INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL),
 563     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 564
 565 END_INIT_SIM_OBJECT_PARAMS(IdeController)
 566
 567 CREATE_SIM_OBJECT(IdeController)
 568 {
 569     return new IdeController(getInstanceName(), intr_ctrl, disks, mmu,
 570                              configspace, configdata, tsunami, pci_bus,
 571                              pci_dev, pci_func, host_bus, hier);
 572 }
 573
 574 REGISTER_SIM_OBJECT("IdeController", IdeController)
 575
 576 #endif //DOXYGEN_SHOULD_SKIP_THIS