2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "base/trace.hh"
35 #include "cpu/intr_control.hh"
37 #include "dev/pcireg.h"
38 #include "dev/pciconfigall.hh"
39 #include "dev/ide_disk.hh"
40 #include "dev/ide_ctrl.hh"
41 #include "dev/tsunami_cchip.hh"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "mem/bus/dma_interface.hh"
46 #include "dev/tsunami.hh"
47 #include "mem/functional_mem/memory_control.hh"
48 #include "mem/functional_mem/physical_memory.hh"
49 #include "sim/builder.hh"
50 #include "sim/sim_object.hh"
55 // Initialization and destruction
58 IdeController::IdeController(const string
&name
, IntrControl
*ic
,
59 const vector
<IdeDisk
*> &new_disks
,
60 MemoryController
*mmu
, PciConfigAll
*cf
,
61 PciConfigData
*cd
, Tsunami
*t
, uint32_t bus_num
,
62 uint32_t dev_num
, uint32_t func_num
,
63 Bus
*host_bus
, HierParams
*hier
)
64 : PciDev(name
, mmu
, cf
, cd
, bus_num
, dev_num
, func_num
), tsunami(t
)
66 // put back pointer into Tsunami
67 tsunami
->disk_controller
= this;
69 // initialize the PIO interface addresses
71 pri_cmd_size
= BARSize
[0];
74 pri_ctrl_size
= BARSize
[1];
77 sec_cmd_size
= BARSize
[2];
80 sec_ctrl_size
= BARSize
[3];
82 // initialize the bus master interface (BMI) address to be configured
85 bmi_size
= BARSize
[4];
87 // zero out all of the registers
88 memset(bmi_regs
, 0, sizeof(bmi_regs
));
89 memset(pci_regs
, 0, sizeof(pci_regs
));
91 // setup initial values
92 *(uint32_t *)&pci_regs
[IDETIM
] = 0x80008000; // enable both channels
93 *(uint8_t *)&bmi_regs
[BMIS0
] = 0x60;
94 *(uint8_t *)&bmi_regs
[BMIS1
] = 0x60;
96 // reset all internal variables
99 memset(cmd_in_progress
, 0, sizeof(cmd_in_progress
));
101 // create the PIO and DMA interfaces
103 pioInterface
= newPioInterface(name
, hier
, host_bus
, this,
104 &IdeController::cacheAccess
);
106 dmaInterface
= new DMAInterface
<Bus
>(name
+ ".dma", host_bus
,
110 // setup the disks attached to controller
111 memset(disks
, 0, sizeof(IdeDisk
*) * 4);
113 if (new_disks
.size() > 3)
114 panic("IDE controllers support a maximum of 4 devices attached!\n");
116 for (int i
= 0; i
< new_disks
.size(); i
++) {
117 disks
[i
] = new_disks
[i
];
118 disks
[i
]->setController(this, dmaInterface
);
122 IdeController::~IdeController()
124 for (int i
= 0; i
< 4; i
++)
134 IdeController::parseAddr(const Addr
&addr
, Addr
&offset
, bool &primary
,
139 if (addr
>= pri_cmd_addr
&& addr
< (pri_cmd_addr
+ pri_cmd_size
)) {
140 offset
-= pri_cmd_addr
;
141 type
= COMMAND_BLOCK
;
143 } else if (addr
>= pri_ctrl_addr
&&
144 addr
< (pri_ctrl_addr
+ pri_ctrl_size
)) {
145 offset
-= pri_ctrl_addr
;
146 type
= CONTROL_BLOCK
;
148 } else if (addr
>= sec_cmd_addr
&&
149 addr
< (sec_cmd_addr
+ sec_cmd_size
)) {
150 offset
-= sec_cmd_addr
;
151 type
= COMMAND_BLOCK
;
153 } else if (addr
>= sec_ctrl_addr
&&
154 addr
< (sec_ctrl_addr
+ sec_ctrl_size
)) {
155 offset
-= sec_ctrl_addr
;
156 type
= CONTROL_BLOCK
;
158 } else if (addr
>= bmi_addr
&& addr
< (bmi_addr
+ bmi_size
)) {
161 primary
= (offset
< BMIC1
) ? true : false;
163 panic("IDE controller access to invalid address: %#x\n", addr
);
168 IdeController::getDisk(bool primary
)
171 uint8_t *devBit
= &dev
[0];
180 assert(*devBit
== 0 || *devBit
== 1);
186 IdeController::getDisk(IdeDisk
*diskPtr
)
188 for (int i
= 0; i
< 4; i
++) {
189 if ((long)diskPtr
== (long)disks
[i
])
196 // Command completion
200 IdeController::setDmaComplete(IdeDisk
*disk
)
202 int diskNum
= getDisk(disk
);
205 panic("Unable to find disk based on pointer %#x\n", disk
);
208 // clear the start/stop bit in the command register
209 bmi_regs
[BMIC0
] &= ~SSBM
;
210 // clear the bus master active bit in the status register
211 bmi_regs
[BMIS0
] &= ~BMIDEA
;
212 // set the interrupt bit
213 bmi_regs
[BMIS0
] |= IDEINTS
;
215 // clear the start/stop bit in the command register
216 bmi_regs
[BMIC1
] &= ~SSBM
;
217 // clear the bus master active bit in the status register
218 bmi_regs
[BMIS1
] &= ~BMIDEA
;
219 // set the interrupt bit
220 bmi_regs
[BMIS1
] |= IDEINTS
;
225 // Interrupt handling
229 IdeController::intrPost()
231 tsunami
->cchip
->postDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
235 IdeController::intrClear()
237 tsunami
->cchip
->clearDRIR(configData
->config
.hdr
.pci0
.interruptLine
);
241 // Bus timing and bus access functions
245 IdeController::cacheAccess(MemReqPtr
&req
)
247 // @todo Add more accurate timing to cache access
248 return curTick
+ 1000;
252 // Read and write handling
256 IdeController::ReadConfig(int offset
, int size
, uint8_t *data
)
258 Addr origOffset
= offset
;
260 if (offset
< PCI_DEVICE_SPECIFIC
) {
261 PciDev::ReadConfig(offset
, size
, data
);
263 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
264 offset
-= PCI_IDE_TIMING
;
267 if ((offset
+ size
) > (IDETIM
+ 4))
268 panic("PCI read of IDETIM with invalid size\n");
269 } else if (offset
== PCI_SLAVE_TIMING
) {
270 offset
-= PCI_SLAVE_TIMING
;
273 if ((offset
+ size
) > (SIDETIM
+ 1))
274 panic("PCI read of SIDETIM with invalid size\n");
275 } else if (offset
== PCI_UDMA33_CTRL
) {
276 offset
-= PCI_UDMA33_CTRL
;
279 if ((offset
+ size
) > (UDMACTL
+ 1))
280 panic("PCI read of UDMACTL with invalid size\n");
281 } else if (offset
>= PCI_UDMA33_TIMING
&&
282 offset
< (PCI_UDMA33_TIMING
+ 2)) {
283 offset
-= PCI_UDMA33_TIMING
;
286 if ((offset
+ size
) > (UDMATIM
+ 2))
287 panic("PCI read of UDMATIM with invalid size\n");
289 panic("PCI read of unimplemented register: %x\n", offset
);
292 memcpy((void *)data
, (void *)&pci_regs
[offset
], size
);
295 DPRINTF(IdeCtrl
, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n",
296 origOffset
, offset
, size
, *(uint32_t *)data
);
300 IdeController::WriteConfig(int offset
, int size
, uint32_t data
)
302 DPRINTF(IdeCtrl
, "IDE PCI write offset: %#x size: %#x data: %#x\n",
305 // do standard write stuff if in standard PCI space
306 if (offset
< PCI_DEVICE_SPECIFIC
) {
307 PciDev::WriteConfig(offset
, size
, data
);
309 if (offset
>= PCI_IDE_TIMING
&& offset
< (PCI_IDE_TIMING
+ 4)) {
310 offset
-= PCI_IDE_TIMING
;
313 if ((offset
+ size
) > (IDETIM
+ 4))
314 panic("PCI write to IDETIM with invalid size\n");
315 } else if (offset
== PCI_SLAVE_TIMING
) {
316 offset
-= PCI_SLAVE_TIMING
;
319 if ((offset
+ size
) > (SIDETIM
+ 1))
320 panic("PCI write to SIDETIM with invalid size\n");
321 } else if (offset
== PCI_UDMA33_CTRL
) {
322 offset
-= PCI_UDMA33_CTRL
;
325 if ((offset
+ size
) > (UDMACTL
+ 1))
326 panic("PCI write to UDMACTL with invalid size\n");
327 } else if (offset
>= PCI_UDMA33_TIMING
&&
328 offset
< (PCI_UDMA33_TIMING
+ 2)) {
329 offset
-= PCI_UDMA33_TIMING
;
332 if ((offset
+ size
) > (UDMATIM
+ 2))
333 panic("PCI write to UDMATIM with invalid size\n");
335 panic("PCI write to unimplemented register: %x\n", offset
);
338 memcpy((void *)&pci_regs
[offset
], (void *)&data
, size
);
341 // Catch the writes to specific PCI registers that have side affects
342 // (like updating the PIO ranges)
345 if (config
.data
[offset
] & IOSE
)
350 if (config
.data
[offset
] & BME
)
356 case PCI0_BASE_ADDR0
:
357 if (BARAddrs
[0] != 0) {
358 pri_cmd_addr
= BARAddrs
[0];
360 pioInterface
->addAddrRange(pri_cmd_addr
,
361 pri_cmd_addr
+ pri_cmd_size
- 1);
363 pri_cmd_addr
&= PA_UNCACHED_MASK
;
367 case PCI0_BASE_ADDR1
:
368 if (BARAddrs
[1] != 0) {
369 pri_ctrl_addr
= BARAddrs
[1];
371 pioInterface
->addAddrRange(pri_ctrl_addr
,
372 pri_ctrl_addr
+ pri_ctrl_size
- 1);
374 pri_ctrl_addr
&= PA_UNCACHED_MASK
;
378 case PCI0_BASE_ADDR2
:
379 if (BARAddrs
[2] != 0) {
380 sec_cmd_addr
= BARAddrs
[2];
382 pioInterface
->addAddrRange(sec_cmd_addr
,
383 sec_cmd_addr
+ sec_cmd_size
- 1);
385 sec_cmd_addr
&= PA_UNCACHED_MASK
;
389 case PCI0_BASE_ADDR3
:
390 if (BARAddrs
[3] != 0) {
391 sec_ctrl_addr
= BARAddrs
[3];
393 pioInterface
->addAddrRange(sec_ctrl_addr
,
394 sec_ctrl_addr
+ sec_ctrl_size
- 1);
396 sec_ctrl_addr
&= PA_UNCACHED_MASK
;
400 case PCI0_BASE_ADDR4
:
401 if (BARAddrs
[4] != 0) {
402 bmi_addr
= BARAddrs
[4];
404 pioInterface
->addAddrRange(bmi_addr
, bmi_addr
+ bmi_size
- 1);
406 bmi_addr
&= PA_UNCACHED_MASK
;
413 IdeController::read(MemReqPtr
&req
, uint8_t *data
)
422 parseAddr(req
->paddr
, offset
, primary
, type
);
423 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
424 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
429 // sanity check the size (allows byte, word, or dword access)
430 if (req
->size
!= sizeof(uint8_t) && req
->size
!= sizeof(uint16_t) &&
431 req
->size
!= sizeof(uint32_t))
432 panic("IDE controller read of invalid size: %#x\n", req
->size
);
434 if (type
!= BMI_BLOCK
) {
435 assert(req
->size
!= sizeof(uint32_t));
437 disk
= getDisk(primary
);
439 disks
[disk
]->read(offset
, byte
, cmdBlk
, data
);
441 memcpy((void *)data
, &bmi_regs
[offset
], req
->size
);
444 DPRINTF(IdeCtrl
, "IDE read from offset: %#x size: %#x data: %#x\n",
445 offset
, req
->size
, *(uint32_t *)data
);
451 IdeController::write(MemReqPtr
&req
, const uint8_t *data
)
460 parseAddr(req
->paddr
, offset
, primary
, type
);
461 byte
= (req
->size
== sizeof(uint8_t)) ? true : false;
462 cmdBlk
= (type
== COMMAND_BLOCK
) ? true : false;
464 DPRINTF(IdeCtrl
, "IDE write from offset: %#x size: %#x data: %#x\n",
465 offset
, req
->size
, *(uint32_t *)data
);
467 uint8_t oldVal
, newVal
;
472 if (type
== BMI_BLOCK
&& !bm_enabled
)
475 if (type
!= BMI_BLOCK
) {
476 // shadow the dev bit
477 if (type
== COMMAND_BLOCK
&& offset
== IDE_SELECT_OFFSET
) {
478 uint8_t *devBit
= (primary
? &dev
[0] : &dev
[1]);
479 *devBit
= ((*data
& IDE_SELECT_DEV_BIT
) ? 1 : 0);
482 assert(req
->size
!= sizeof(uint32_t));
484 disk
= getDisk(primary
);
486 disks
[disk
]->write(offset
, byte
, cmdBlk
, data
);
489 // Bus master IDE command register
492 if (req
->size
!= sizeof(uint8_t))
493 panic("Invalid BMIC write size: %x\n", req
->size
);
495 // select the current disk based on DEV bit
496 disk
= getDisk(primary
);
498 oldVal
= bmi_regs
[offset
];
501 // if a DMA transfer is in progress, R/W control cannot change
503 if ((oldVal
& RWCON
) ^ (newVal
& RWCON
)) {
504 (oldVal
& RWCON
) ? newVal
|= RWCON
: newVal
&= ~RWCON
;
508 // see if the start/stop bit is being changed
509 if ((oldVal
& SSBM
) ^ (newVal
& SSBM
)) {
511 // stopping DMA transfer
512 DPRINTF(IdeCtrl
, "Stopping DMA transfer\n");
514 // clear the BMIDEA bit
515 bmi_regs
[offset
+ 0x2] &= ~BMIDEA
;
517 if (disks
[disk
] == NULL
)
518 panic("DMA stop for disk %d which does not exist\n",
521 // inform the disk of the DMA transfer abort
522 disks
[disk
]->abortDma();
524 // starting DMA transfer
525 DPRINTF(IdeCtrl
, "Starting DMA transfer\n");
527 // set the BMIDEA bit
528 bmi_regs
[offset
+ 0x2] |= BMIDEA
;
530 if (disks
[disk
] == NULL
)
531 panic("DMA start for disk %d which does not exist\n",
534 // inform the disk of the DMA transfer start
536 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP0
]);
538 disks
[disk
]->startDma(*(uint32_t *)&bmi_regs
[BMIDTP1
]);
542 // update the register value
543 bmi_regs
[offset
] = newVal
;
546 // Bus master IDE status register
549 if (req
->size
!= sizeof(uint8_t))
550 panic("Invalid BMIS write size: %x\n", req
->size
);
552 oldVal
= bmi_regs
[offset
];
555 // the BMIDEA bit is RO
556 newVal
|= (oldVal
& BMIDEA
);
558 // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
559 if ((oldVal
& IDEINTS
) && (newVal
& IDEINTS
))
560 newVal
&= ~IDEINTS
; // clear the interrupt?
562 (oldVal
& IDEINTS
) ? newVal
|= IDEINTS
: newVal
&= ~IDEINTS
;
564 if ((oldVal
& IDEDMAE
) && (newVal
& IDEDMAE
))
567 (oldVal
& IDEDMAE
) ? newVal
|= IDEDMAE
: newVal
&= ~IDEDMAE
;
569 bmi_regs
[offset
] = newVal
;
572 // Bus master IDE descriptor table pointer register
575 if (req
->size
!= sizeof(uint32_t))
576 panic("Invalid BMIDTP write size: %x\n", req
->size
);
578 *(uint32_t *)&bmi_regs
[offset
] = *(uint32_t *)data
& ~0x3;
582 if (req
->size
!= sizeof(uint8_t) &&
583 req
->size
!= sizeof(uint16_t) &&
584 req
->size
!= sizeof(uint32_t))
585 panic("IDE controller write of invalid write size: %x\n",
588 // do a default copy of data into the registers
589 memcpy((void *)&bmi_regs
[offset
], data
, req
->size
);
601 IdeController::serialize(std::ostream
&os
)
603 // Serialize the PciDev base class
604 PciDev::serialize(os
);
606 // Serialize register addresses and sizes
607 SERIALIZE_SCALAR(pri_cmd_addr
);
608 SERIALIZE_SCALAR(pri_cmd_size
);
609 SERIALIZE_SCALAR(pri_ctrl_addr
);
610 SERIALIZE_SCALAR(pri_ctrl_size
);
611 SERIALIZE_SCALAR(sec_cmd_addr
);
612 SERIALIZE_SCALAR(sec_cmd_size
);
613 SERIALIZE_SCALAR(sec_ctrl_addr
);
614 SERIALIZE_SCALAR(sec_ctrl_size
);
615 SERIALIZE_SCALAR(bmi_addr
);
616 SERIALIZE_SCALAR(bmi_size
);
618 // Serialize registers
619 SERIALIZE_ARRAY(bmi_regs
, 16);
620 SERIALIZE_ARRAY(dev
, 2);
621 SERIALIZE_ARRAY(pci_regs
, 8);
623 // Serialize internal state
624 SERIALIZE_SCALAR(io_enabled
);
625 SERIALIZE_SCALAR(bm_enabled
);
626 SERIALIZE_ARRAY(cmd_in_progress
, 4);
630 IdeController::unserialize(Checkpoint
*cp
, const std::string
§ion
)
632 // Unserialize the PciDev base class
633 PciDev::unserialize(cp
, section
);
635 // Unserialize register addresses and sizes
636 UNSERIALIZE_SCALAR(pri_cmd_addr
);
637 UNSERIALIZE_SCALAR(pri_cmd_size
);
638 UNSERIALIZE_SCALAR(pri_ctrl_addr
);
639 UNSERIALIZE_SCALAR(pri_ctrl_size
);
640 UNSERIALIZE_SCALAR(sec_cmd_addr
);
641 UNSERIALIZE_SCALAR(sec_cmd_size
);
642 UNSERIALIZE_SCALAR(sec_ctrl_addr
);
643 UNSERIALIZE_SCALAR(sec_ctrl_size
);
644 UNSERIALIZE_SCALAR(bmi_addr
);
645 UNSERIALIZE_SCALAR(bmi_size
);
647 // Unserialize registers
648 UNSERIALIZE_ARRAY(bmi_regs
, 16);
649 UNSERIALIZE_ARRAY(dev
, 2);
650 UNSERIALIZE_ARRAY(pci_regs
, 8);
652 // Unserialize internal state
653 UNSERIALIZE_SCALAR(io_enabled
);
654 UNSERIALIZE_SCALAR(bm_enabled
);
655 UNSERIALIZE_ARRAY(cmd_in_progress
, 4);
658 #ifndef DOXYGEN_SHOULD_SKIP_THIS
660 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
662 SimObjectParam
<IntrControl
*> intr_ctrl
;
663 SimObjectVectorParam
<IdeDisk
*> disks
;
664 SimObjectParam
<MemoryController
*> mmu
;
665 SimObjectParam
<PciConfigAll
*> configspace
;
666 SimObjectParam
<PciConfigData
*> configdata
;
667 SimObjectParam
<Tsunami
*> tsunami
;
668 Param
<uint32_t> pci_bus
;
669 Param
<uint32_t> pci_dev
;
670 Param
<uint32_t> pci_func
;
671 SimObjectParam
<Bus
*> host_bus
;
672 SimObjectParam
<HierParams
*> hier
;
674 END_DECLARE_SIM_OBJECT_PARAMS(IdeController
)
676 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController
)
678 INIT_PARAM(intr_ctrl
, "Interrupt Controller"),
679 INIT_PARAM(disks
, "IDE disks attached to this controller"),
680 INIT_PARAM(mmu
, "Memory controller"),
681 INIT_PARAM(configspace
, "PCI Configspace"),
682 INIT_PARAM(configdata
, "PCI Config data"),
683 INIT_PARAM(tsunami
, "Tsunami chipset pointer"),
684 INIT_PARAM(pci_bus
, "PCI bus ID"),
685 INIT_PARAM(pci_dev
, "PCI device number"),
686 INIT_PARAM(pci_func
, "PCI function code"),
687 INIT_PARAM_DFLT(host_bus
, "Host bus to attach to", NULL
),
688 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
690 END_INIT_SIM_OBJECT_PARAMS(IdeController
)
692 CREATE_SIM_OBJECT(IdeController
)
694 return new IdeController(getInstanceName(), intr_ctrl
, disks
, mmu
,
695 configspace
, configdata
, tsunami
, pci_bus
,
696 pci_dev
, pci_func
, host_bus
, hier
);
699 REGISTER_SIM_OBJECT("IdeController", IdeController
)
701 #endif //DOXYGEN_SHOULD_SKIP_THIS