2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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30 * Simple PCI IDE controller with bus mastering capability and UDMA
31 * modeled after controller in the Intel PIIX4 chip
34 #ifndef __IDE_CTRL_HH__
35 #define __IDE_CTRL_HH__
37 #include "dev/pcidev.hh"
38 #include "dev/pcireg.h"
39 #include "dev/io_device.hh"
41 #define BMIC0 0x0 // Bus master IDE command register
42 #define BMIS0 0x2 // Bus master IDE status register
43 #define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
44 #define BMIC1 0x8 // Bus master IDE command register
45 #define BMIS1 0xa // Bus master IDE status register
46 #define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
48 // Bus master IDE command register bit fields
49 #define RWCON 0x08 // Bus master read/write control
50 #define SSBM 0x01 // Start/stop bus master
52 // Bus master IDE status register bit fields
53 #define DMA1CAP 0x40 // Drive 1 DMA capable
54 #define DMA0CAP 0x20 // Drive 0 DMA capable
55 #define IDEINTS 0x04 // IDE Interrupt Status
56 #define IDEDMAE 0x02 // IDE DMA error
57 #define BMIDEA 0x01 // Bus master IDE active
59 // IDE Command byte fields
60 #define IDE_SELECT_OFFSET (6)
61 #define IDE_SELECT_DEV_BIT 0x10
63 #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
64 #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
66 // IDE Timing Register bit fields
67 #define IDETIM_DECODE_EN 0x8000
69 // PCI device specific register byte offsets
70 #define IDE_CTRL_CONF_START 0x40
71 #define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
90 * Device model for an Intel PIIX4 IDE controller
93 class IdeController : public PciDev
103 /** Primary command block registers */
106 /** Primary control block registers */
109 /** Secondary command block registers */
112 /** Secondary control block registers */
115 /** Bus master interface (BMI) registers */
120 /** Registers used for bus master interface */
146 /** Shadows of the device select bit */
148 /** Registers used in device specific PCI configuration */
156 uint8_t reserved_0[3];
160 uint8_t reserved_2[8];
165 // Internal management variables
168 bool cmd_in_progress[4];
171 /** IDE disks connected to controller */
175 /** Parse the access address to pass on to device */
176 void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
177 IdeRegType ®_type);
179 /** Select the disk based on the channel and device bit */
180 int getDisk(IdeChannel channel);
182 /** Select the disk based on a pointer */
183 int getDisk(IdeDisk *diskPtr);
186 /** See if a disk is selected based on its pointer */
187 bool isDiskSelected(IdeDisk *diskPtr);
190 struct Params : public PciDev::Params
192 /** Array of disk objects */
193 std::vector<IdeDisk *> disks;
199 const Params *params() const { return (const Params *)_params; }
202 IdeController(Params *p);
205 virtual void writeConfig(int offset, int size, const uint8_t *data);
206 virtual void readConfig(int offset, int size, uint8_t *data);
208 void setDmaComplete(IdeDisk *disk);
211 * Read a done field for a given target.
212 * @param req Contains the address of the field to read.
213 * @param data Return the field read.
214 * @return The fault condition of the access.
216 virtual Fault read(MemReqPtr &req, uint8_t *data);
219 * Write to the mmapped I/O control registers.
220 * @param req Contains the address to write to.
221 * @param data The data to write.
222 * @return The fault condition of the access.
224 virtual Fault write(MemReqPtr &req, const uint8_t *data);
227 * Serialize this object to the given output stream.
228 * @param os The stream to serialize to.
230 virtual void serialize(std::ostream &os);
233 * Reconstruct the state of this object from a checkpoint.
234 * @param cp The checkpoint use.
235 * @param section The section name of this object
237 virtual void unserialize(Checkpoint *cp, const std::string §ion);
240 * Return how long this access will take.
241 * @param req the memory request to calcuate
242 * @return Tick when the request is done
244 Tick cacheAccess(MemReqPtr &req);
246 #endif // __IDE_CTRL_HH_