2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Simple PCI IDE controller with bus mastering capability and UDMA
31 * modeled after controller in the Intel PIIX4 chip
34 #ifndef __IDE_CTRL_HH__
35 #define __IDE_CTRL_HH__
37 #include "dev/pcidev.hh"
38 #include "dev/pcireg.h"
39 #include "dev/io_device.hh"
41 #define BMIC0 0x0 // Bus master IDE command register
42 #define BMIS0 0x2 // Bus master IDE status register
43 #define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
44 #define BMIC1 0x8 // Bus master IDE command register
45 #define BMIS1 0xa // Bus master IDE status register
46 #define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
48 // Bus master IDE command register bit fields
49 #define RWCON 0x08 // Bus master read/write control
50 #define SSBM 0x01 // Start/stop bus master
52 // Bus master IDE status register bit fields
53 #define DMA1CAP 0x40 // Drive 1 DMA capable
54 #define DMA0CAP 0x20 // Drive 0 DMA capable
55 #define IDEINTS 0x04 // IDE Interrupt Status
56 #define IDEDMAE 0x02 // IDE DMA error
57 #define BMIDEA 0x01 // Bus master IDE active
59 // IDE Command byte fields
60 #define IDE_SELECT_OFFSET (6)
61 #define IDE_SELECT_DEV_BIT 0x10
63 #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
64 #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
66 // PCI device specific register byte offsets
67 #define PCI_IDE_TIMING 0x40
68 #define PCI_SLAVE_TIMING 0x44
69 #define PCI_UDMA33_CTRL 0x48
70 #define PCI_UDMA33_TIMING 0x4a
77 // PCI Command bit fields
78 #define BME 0x04 // Bus master function enable
79 #define IOSE 0x01 // I/O space enable
81 typedef enum RegType {
97 * Device model for an Intel PIIX4 IDE controller
100 class IdeController : public PciDev
103 /** Primary command block registers */
106 /** Primary control block registers */
109 /** Secondary command block registers */
112 /** Secondary control block registers */
115 /** Bus master interface (BMI) registers */
120 /** Registers used for bus master interface */
121 uint8_t bmi_regs[16];
122 /** Shadows of the device select bit */
124 /** Registers used in PCI configuration */
127 // Internal management variables
130 bool cmd_in_progress[4];
133 /** Pointer to the chipset */
137 /** IDE disks connected to controller */
141 /** Parse the access address to pass on to device */
142 void parseAddr(const Addr &addr, Addr &offset, bool &primary,
145 /** Select the disk based on the channel and device bit */
146 int getDisk(bool primary);
148 /** Select the disk based on a pointer */
149 int getDisk(IdeDisk *diskPtr);
153 * Constructs and initializes this controller.
154 * @param name The name of this controller.
155 * @param ic The interrupt controller.
156 * @param mmu The memory controller
157 * @param cf PCI config space
158 * @param cd PCI config data
159 * @param bus_num The PCI bus number
160 * @param dev_num The PCI device number
161 * @param func_num The PCI function number
162 * @param host_bus The host bus to connect to
163 * @param hier The hierarchy parameters
165 IdeController(const std::string &name, IntrControl *ic,
166 const std::vector<IdeDisk *> &new_disks,
167 MemoryController *mmu, PciConfigAll *cf,
168 PciConfigData *cd, Tsunami *t,
169 uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
170 Bus *host_bus, HierParams *hier);
173 * Deletes the connected devices.
177 virtual void WriteConfig(int offset, int size, uint32_t data);
178 virtual void ReadConfig(int offset, int size, uint8_t *data);
183 void setDmaComplete(IdeDisk *disk);
186 * Read a done field for a given target.
187 * @param req Contains the address of the field to read.
188 * @param data Return the field read.
189 * @return The fault condition of the access.
191 virtual Fault read(MemReqPtr &req, uint8_t *data);
194 * Write to the mmapped I/O control registers.
195 * @param req Contains the address to write to.
196 * @param data The data to write.
197 * @return The fault condition of the access.
199 virtual Fault write(MemReqPtr &req, const uint8_t *data);
202 * Serialize this object to the given output stream.
203 * @param os The stream to serialize to.
205 virtual void serialize(std::ostream &os);
208 * Reconstruct the state of this object from a checkpoint.
209 * @param cp The checkpoint use.
210 * @param section The section name of this object
212 virtual void unserialize(Checkpoint *cp, const std::string §ion);
215 * Return how long this access will take.
216 * @param req the memory request to calcuate
217 * @return Tick when the request is done
219 Tick cacheAccess(MemReqPtr &req);
221 #endif // __IDE_CTRL_HH_