2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Simple PCI IDE controller with bus mastering capability and UDMA
31 * modeled after controller in the Intel PIIX4 chip
34 #ifndef __IDE_CTRL_HH__
35 #define __IDE_CTRL_HH__
37 #include "dev/pcidev.hh"
38 #include "dev/pcireg.h"
39 #include "dev/io_device.hh"
41 #define BMIC0 0x0 // Bus master IDE command register
42 #define BMIS0 0x2 // Bus master IDE status register
43 #define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register
44 #define BMIC1 0x8 // Bus master IDE command register
45 #define BMIS1 0xa // Bus master IDE status register
46 #define BMIDTP1 0xc // Bus master IDE descriptor table pointer register
48 // Bus master IDE command register bit fields
49 #define RWCON 0x08 // Bus master read/write control
50 #define SSBM 0x01 // Start/stop bus master
52 // Bus master IDE status register bit fields
53 #define DMA1CAP 0x40 // Drive 1 DMA capable
54 #define DMA0CAP 0x20 // Drive 0 DMA capable
55 #define IDEINTS 0x04 // IDE Interrupt Status
56 #define IDEDMAE 0x02 // IDE DMA error
57 #define BMIDEA 0x01 // Bus master IDE active
59 // IDE Command byte fields
60 #define IDE_SELECT_OFFSET (6)
61 #define IDE_SELECT_DEV_BIT 0x10
63 #define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
64 #define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
66 // PCI device specific register byte offsets
67 #define PCI_IDE_TIMING 0x40
68 #define PCI_SLAVE_TIMING 0x44
69 #define PCI_UDMA33_CTRL 0x48
70 #define PCI_UDMA33_TIMING 0x4a
77 typedef enum RegType {
93 * Device model for an Intel PIIX4 IDE controller
96 class IdeController : public PciDev
101 /** Primary command block registers */
104 /** Primary control block registers */
107 /** Secondary command block registers */
110 /** Secondary control block registers */
113 /** Bus master interface (BMI) registers */
118 /** Registers used for bus master interface */
119 uint8_t bmi_regs[16];
120 /** Shadows of the device select bit */
122 /** Registers used in PCI configuration */
125 // Internal management variables
128 bool cmd_in_progress[4];
131 /** IDE disks connected to controller */
135 /** Parse the access address to pass on to device */
136 void parseAddr(const Addr &addr, Addr &offset, bool &primary,
139 /** Select the disk based on the channel and device bit */
140 int getDisk(bool primary);
142 /** Select the disk based on a pointer */
143 int getDisk(IdeDisk *diskPtr);
146 /** See if a disk is selected based on its pointer */
147 bool isDiskSelected(IdeDisk *diskPtr);
150 struct Params : public PciDev::Params
152 /** Array of disk objects */
153 std::vector<IdeDisk *> disks;
158 const Params *params() const { return (const Params *)_params; }
161 IdeController(Params *p);
164 virtual void WriteConfig(int offset, int size, uint32_t data);
165 virtual void ReadConfig(int offset, int size, uint8_t *data);
167 void setDmaComplete(IdeDisk *disk);
170 * Read a done field for a given target.
171 * @param req Contains the address of the field to read.
172 * @param data Return the field read.
173 * @return The fault condition of the access.
175 virtual Fault read(MemReqPtr &req, uint8_t *data);
178 * Write to the mmapped I/O control registers.
179 * @param req Contains the address to write to.
180 * @param data The data to write.
181 * @return The fault condition of the access.
183 virtual Fault write(MemReqPtr &req, const uint8_t *data);
186 * Serialize this object to the given output stream.
187 * @param os The stream to serialize to.
189 virtual void serialize(std::ostream &os);
192 * Reconstruct the state of this object from a checkpoint.
193 * @param cp The checkpoint use.
194 * @param section The section name of this object
196 virtual void unserialize(Checkpoint *cp, const std::string §ion);
199 * Return how long this access will take.
200 * @param req the memory request to calcuate
201 * @return Tick when the request is done
203 Tick cacheAccess(MemReqPtr &req);
205 #endif // __IDE_CTRL_HH_