2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Device model implementation for an IDE disk
38 #include "base/cprintf.hh" // csprintf
39 #include "base/trace.hh"
40 #include "dev/disk_image.hh"
41 #include "dev/ide_disk.hh"
42 #include "dev/ide_ctrl.hh"
43 #include "dev/tsunami.hh"
44 #include "dev/tsunami_pchip.hh"
45 #include "mem/functional_mem/physical_memory.hh"
46 #include "mem/bus/bus.hh"
47 #include "mem/bus/dma_interface.hh"
48 #include "mem/bus/pio_interface.hh"
49 #include "mem/bus/pio_interface_impl.hh"
50 #include "sim/builder.hh"
51 #include "sim/sim_object.hh"
52 #include "sim/universe.hh"
53 #include "targetarch/isa_traits.hh"
57 IdeDisk::IdeDisk(const string
&name
, DiskImage
*img
, PhysicalMemory
*phys
,
59 : SimObject(name
), ctrl(NULL
), image(img
), physmem(phys
),
60 dmaTransferEvent(this), dmaReadWaitEvent(this),
61 dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
62 dmaReadEvent(this), dmaWriteEvent(this)
64 // Reset the device state
67 // calculate disk delay in microseconds
68 diskDelay
= (delay
* ticksPerSecond
/ 100000);
70 // fill out the drive ID structure
71 memset(&driveID
, 0, sizeof(struct hd_driveid
));
73 // Calculate LBA and C/H/S values
78 uint32_t lba_size
= image
->size();
79 if (lba_size
>= 16383*16*63) {
89 if ((lba_size
/ sectors
) >= 16)
92 heads
= (lba_size
/ sectors
);
94 cylinders
= lba_size
/ (heads
* sectors
);
97 // Setup the model name
98 sprintf((char *)driveID
.model
, "5MI EDD si k");
99 // Set the maximum multisector transfer size
100 driveID
.max_multsect
= MAX_MULTSECT
;
101 // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
102 driveID
.capability
= 0x7;
103 // UDMA support, EIDE support
104 driveID
.field_valid
= 0x6;
105 // Setup default C/H/S settings
106 driveID
.cyls
= cylinders
;
107 driveID
.sectors
= sectors
;
108 driveID
.heads
= heads
;
109 // Setup the current multisector transfer size
110 driveID
.multsect
= MAX_MULTSECT
;
111 driveID
.multsect_valid
= 0x1;
112 // Number of sectors on disk
113 driveID
.lba_capacity
= lba_size
;
114 // Multiword DMA mode 2 and below supported
115 driveID
.dma_mword
= 0x400;
116 // Set PIO mode 4 and 3 supported
117 driveID
.eide_pio_modes
= 0x3;
118 // Set DMA mode 4 and below supported
119 driveID
.dma_ultra
= 0x10;
120 // Statically set hardware config word
121 driveID
.hw_config
= 0x4001;
126 // destroy the data buffer
127 delete [] dataBuffer
;
131 IdeDisk::reset(int id
)
133 // initialize the data buffer and shadow registers
134 dataBuffer
= new uint8_t[MAX_DMA_SIZE
];
136 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
137 memset(&cmdReg
, 0, sizeof(CommandReg_t
));
138 memset(&curPrd
.entry
, 0, sizeof(PrdEntry_t
));
140 dmaInterfaceBytes
= 0;
149 // set the device state to idle
153 devState
= Device_Idle_S
;
155 } else if (id
== DEV1
) {
156 devState
= Device_Idle_NS
;
159 panic("Invalid device ID: %#x\n", id
);
162 // set the device ready bit
163 status
= STATUS_DRDY_BIT
;
171 IdeDisk::isDEVSelect()
173 return ctrl
->isDiskSelected(this);
177 IdeDisk::pciToDma(Addr pciAddr
)
180 return ctrl
->plat
->pciToDma(pciAddr
);
182 panic("Access to unset controller!\n");
186 IdeDisk::bytesInDmaPage(Addr curAddr
, uint32_t bytesLeft
)
188 uint32_t bytesInPage
= 0;
190 // First calculate how many bytes could be in the page
191 if (bytesLeft
> TheISA::PageBytes
)
192 bytesInPage
= TheISA::PageBytes
;
194 bytesInPage
= bytesLeft
;
196 // Next, see if we have crossed a page boundary, and adjust
197 Addr upperBound
= curAddr
+ bytesInPage
;
198 Addr pageBound
= TheISA::TruncPage(curAddr
) + TheISA::PageBytes
;
200 assert(upperBound
>= curAddr
&& "DMA read wraps around address space!\n");
202 if (upperBound
>= pageBound
)
203 bytesInPage
= pageBound
- curAddr
;
209 // Device registers read/write
213 IdeDisk::read(const Addr
&offset
, bool byte
, bool cmdBlk
, uint8_t *data
)
215 DevAction_t action
= ACT_NONE
;
218 if (offset
< 0 || offset
> sizeof(CommandReg_t
))
219 panic("Invalid disk command register offset: %#x\n", offset
);
221 if (!byte
&& offset
!= DATA_OFFSET
)
222 panic("Invalid 16-bit read, only allowed on data reg\n");
225 *(uint16_t *)data
= *(uint16_t *)&cmdReg
.data0
;
227 *data
= ((uint8_t *)&cmdReg
)[offset
];
229 // determine if an action needs to be taken on the state machine
230 if (offset
== STATUS_OFFSET
) {
231 action
= ACT_STAT_READ
;
232 *data
= status
; // status is in a shadow, explicity copy
233 } else if (offset
== DATA_OFFSET
) {
235 action
= ACT_DATA_READ_BYTE
;
237 action
= ACT_DATA_READ_SHORT
;
241 if (offset
!= ALTSTAT_OFFSET
)
242 panic("Invalid disk control register offset: %#x\n", offset
);
245 panic("Invalid 16-bit read from control block\n");
250 if (action
!= ACT_NONE
)
255 IdeDisk::write(const Addr
&offset
, bool byte
, bool cmdBlk
, const uint8_t *data
)
257 DevAction_t action
= ACT_NONE
;
260 if (offset
< 0 || offset
> sizeof(CommandReg_t
))
261 panic("Invalid disk command register offset: %#x\n", offset
);
263 if (!byte
&& offset
!= DATA_OFFSET
)
264 panic("Invalid 16-bit write, only allowed on data reg\n");
267 *((uint16_t *)&cmdReg
.data0
) = *(uint16_t *)data
;
269 ((uint8_t *)&cmdReg
)[offset
] = *data
;
271 // determine if an action needs to be taken on the state machine
272 if (offset
== COMMAND_OFFSET
) {
273 action
= ACT_CMD_WRITE
;
274 } else if (offset
== DATA_OFFSET
) {
276 action
= ACT_DATA_WRITE_BYTE
;
278 action
= ACT_DATA_WRITE_SHORT
;
279 } else if (offset
== SELECT_OFFSET
) {
280 action
= ACT_SELECT_WRITE
;
284 if (offset
!= CONTROL_OFFSET
)
285 panic("Invalid disk control register offset: %#x\n", offset
);
288 panic("Invalid 16-bit write to control block\n");
290 if (*data
& CONTROL_RST_BIT
) {
291 // force the device into the reset state
292 devState
= Device_Srst
;
293 action
= ACT_SRST_SET
;
294 } else if (devState
== Device_Srst
&& !(*data
& CONTROL_RST_BIT
)) {
295 action
= ACT_SRST_CLEAR
;
298 nIENBit
= (*data
& CONTROL_IEN_BIT
) ? true : false;
301 if (action
!= ACT_NONE
)
306 // Perform DMA transactions
310 IdeDisk::doDmaTransfer()
312 if (dmaState
!= Dma_Transfer
|| devState
!= Transfer_Data_Dma
)
313 panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
316 // first read the current PRD
318 if (dmaInterface
->busy()) {
319 // reschedule after waiting period
320 dmaTransferEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
324 dmaInterface
->doDMA(Read
, curPrdAddr
, sizeof(PrdEntry_t
), curTick
,
332 IdeDisk::dmaPrdReadDone()
334 // actually copy the PRD from physical memory
335 memcpy((void *)&curPrd
.entry
,
336 physmem
->dma_addr(curPrdAddr
, sizeof(PrdEntry_t
)),
340 "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
341 curPrd
.getBaseAddr(), pciToDma(curPrd
.getBaseAddr()),
342 curPrd
.getByteCount(), (cmdBytesLeft
/SectorSize
),
343 curPrd
.getEOT(), curSector
);
345 // the prd pointer has already been translated, so just do an increment
346 curPrdAddr
= curPrdAddr
+ sizeof(PrdEntry_t
);
357 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
360 if (dmaInterface
->busy()) {
361 // reschedule after waiting period
362 dmaReadWaitEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
366 Addr dmaAddr
= pciToDma(curPrd
.getBaseAddr());
368 uint32_t bytesInPage
= bytesInDmaPage(curPrd
.getBaseAddr(),
369 (uint32_t)curPrd
.getByteCount());
371 dmaInterfaceBytes
= bytesInPage
;
373 dmaInterface
->doDMA(Read
, dmaAddr
, bytesInPage
,
374 curTick
+ totalDiskDelay
, &dmaReadEvent
);
376 // schedule dmaReadEvent with sectorDelay (dmaReadDone)
377 dmaReadEvent
.schedule(curTick
+ totalDiskDelay
);
382 IdeDisk::dmaReadDone()
385 Addr curAddr
= 0, dmaAddr
= 0;
386 uint32_t bytesWritten
= 0, bytesInPage
= 0, bytesLeft
= 0;
388 // continue to use the DMA interface until all pages are read
389 if (dmaInterface
&& (dmaInterfaceBytes
< curPrd
.getByteCount())) {
390 // see if the interface is busy
391 if (dmaInterface
->busy()) {
392 // reschedule after waiting period
393 dmaReadEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
397 uint32_t bytesLeft
= curPrd
.getByteCount() - dmaInterfaceBytes
;
398 curAddr
= curPrd
.getBaseAddr() + dmaInterfaceBytes
;
399 dmaAddr
= pciToDma(curAddr
);
401 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
402 dmaInterfaceBytes
+= bytesInPage
;
404 dmaInterface
->doDMA(Read
, dmaAddr
, bytesInPage
,
405 curTick
, &dmaReadEvent
);
410 // set initial address
411 curAddr
= curPrd
.getBaseAddr();
413 // clear out the data buffer
414 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
416 // read the data from memory via DMA into a data buffer
417 while (bytesWritten
< curPrd
.getByteCount()) {
418 if (cmdBytesLeft
<= 0)
419 panic("DMA data is larger than # of sectors specified\n");
421 dmaAddr
= pciToDma(curAddr
);
423 // calculate how many bytes are in the current page
424 bytesLeft
= curPrd
.getByteCount() - bytesWritten
;
425 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
427 // copy the data from memory into the data buffer
428 memcpy((void *)(dataBuffer
+ bytesWritten
),
429 physmem
->dma_addr(dmaAddr
, bytesInPage
),
432 curAddr
+= bytesInPage
;
433 bytesWritten
+= bytesInPage
;
434 cmdBytesLeft
-= bytesInPage
;
437 // write the data to the disk image
438 for (bytesWritten
= 0;
439 bytesWritten
< curPrd
.getByteCount();
440 bytesWritten
+= SectorSize
) {
442 writeDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesWritten
));
446 if (curPrd
.getEOT()) {
447 assert(cmdBytesLeft
== 0);
449 updateState(ACT_DMA_DONE
);
456 IdeDisk::doDmaWrite()
458 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
461 if (dmaInterface
->busy()) {
462 // reschedule after waiting period
463 dmaWriteWaitEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
467 Addr dmaAddr
= pciToDma(curPrd
.getBaseAddr());
469 uint32_t bytesInPage
= bytesInDmaPage(curPrd
.getBaseAddr(),
470 (uint32_t)curPrd
.getByteCount());
472 dmaInterfaceBytes
= bytesInPage
;
474 dmaInterface
->doDMA(WriteInvalidate
, dmaAddr
,
475 bytesInPage
, curTick
+ totalDiskDelay
,
478 // schedule event with disk delay (dmaWriteDone)
479 dmaWriteEvent
.schedule(curTick
+ totalDiskDelay
);
484 IdeDisk::dmaWriteDone()
486 Addr curAddr
= 0, pageAddr
= 0, dmaAddr
= 0;
487 uint32_t bytesRead
= 0, bytesInPage
= 0;
489 // continue to use the DMA interface until all pages are read
490 if (dmaInterface
&& (dmaInterfaceBytes
< curPrd
.getByteCount())) {
491 // see if the interface is busy
492 if (dmaInterface
->busy()) {
493 // reschedule after waiting period
494 dmaWriteEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
498 uint32_t bytesLeft
= curPrd
.getByteCount() - dmaInterfaceBytes
;
499 curAddr
= curPrd
.getBaseAddr() + dmaInterfaceBytes
;
500 dmaAddr
= pciToDma(curAddr
);
502 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
503 dmaInterfaceBytes
+= bytesInPage
;
505 dmaInterface
->doDMA(WriteInvalidate
, dmaAddr
,
506 bytesInPage
, curTick
,
512 // setup the initial page and DMA address
513 curAddr
= curPrd
.getBaseAddr();
514 pageAddr
= TheISA::TruncPage(curAddr
);
515 dmaAddr
= pciToDma(curAddr
);
517 // clear out the data buffer
518 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
520 while (bytesRead
< curPrd
.getByteCount()) {
521 // see if we have crossed into a new page
522 if (pageAddr
!= TheISA::TruncPage(curAddr
)) {
523 // write the data to memory
524 memcpy(physmem
->dma_addr(dmaAddr
, bytesInPage
),
525 (void *)(dataBuffer
+ (bytesRead
- bytesInPage
)),
528 // update the DMA address and page address
529 pageAddr
= TheISA::TruncPage(curAddr
);
530 dmaAddr
= pciToDma(curAddr
);
535 if (cmdBytesLeft
<= 0)
536 panic("DMA requested data is larger than # sectors specified\n");
538 readDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesRead
));
540 curAddr
+= SectorSize
;
541 bytesRead
+= SectorSize
;
542 bytesInPage
+= SectorSize
;
543 cmdBytesLeft
-= SectorSize
;
546 // write the last page worth read to memory
547 if (bytesInPage
!= 0) {
548 memcpy(physmem
->dma_addr(dmaAddr
, bytesInPage
),
549 (void *)(dataBuffer
+ (bytesRead
- bytesInPage
)),
554 if (curPrd
.getEOT()) {
555 assert(cmdBytesLeft
== 0);
557 updateState(ACT_DMA_DONE
);
564 // Disk utility routines
568 IdeDisk::readDisk(uint32_t sector
, uint8_t *data
)
570 uint32_t bytesRead
= image
->read(data
, sector
);
572 if (bytesRead
!= SectorSize
)
573 panic("Can't read from %s. Only %d of %d read. errno=%d\n",
574 name(), bytesRead
, SectorSize
, errno
);
578 IdeDisk::writeDisk(uint32_t sector
, uint8_t *data
)
580 uint32_t bytesWritten
= image
->write(data
, sector
);
582 if (bytesWritten
!= SectorSize
)
583 panic("Can't write to %s. Only %d of %d written. errno=%d\n",
584 name(), bytesWritten
, SectorSize
, errno
);
588 // Setup and handle commands
592 IdeDisk::startDma(const uint32_t &prdTableBase
)
594 if (dmaState
!= Dma_Start
)
595 panic("Inconsistent DMA state, should be in Dma_Start!\n");
597 if (devState
!= Transfer_Data_Dma
)
598 panic("Inconsistent device state for DMA start!\n");
600 // PRD base address is given by bits 31:2
601 curPrdAddr
= pciToDma((Addr
)(prdTableBase
& ~ULL(0x3)));
603 dmaState
= Dma_Transfer
;
605 // schedule dma transfer (doDmaTransfer)
606 dmaTransferEvent
.schedule(curTick
+ 1);
612 if (dmaState
== Dma_Idle
)
613 panic("Inconsistent DMA state, should be Start or Transfer!");
615 if (devState
!= Transfer_Data_Dma
&& devState
!= Prepare_Data_Dma
)
616 panic("Inconsistent device state, should be Transfer or Prepare!\n");
618 updateState(ACT_CMD_ERROR
);
622 IdeDisk::startCommand()
624 DevAction_t action
= ACT_NONE
;
629 switch (cmdReg
.command
) {
630 // Supported non-data commands
631 case WIN_READ_NATIVE_MAX
:
632 size
= image
->size() - 1;
633 cmdReg
.sec_num
= (size
& 0xff);
634 cmdReg
.cyl_low
= ((size
& 0xff00) >> 8);
635 cmdReg
.cyl_high
= ((size
& 0xff0000) >> 16);
636 cmdReg
.head
= ((size
& 0xf000000) >> 24);
638 devState
= Command_Execution
;
639 action
= ACT_CMD_COMPLETE
;
644 case WIN_STANDBYNOW1
:
645 case WIN_FLUSH_CACHE
:
648 case WIN_SETFEATURES
:
650 devState
= Command_Execution
;
651 action
= ACT_CMD_COMPLETE
;
654 // Supported PIO data-in commands
656 cmdBytes
= cmdBytesLeft
= sizeof(struct hd_driveid
);
657 devState
= Prepare_Data_In
;
658 action
= ACT_DATA_READY
;
663 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
664 panic("Attempt to perform CHS access, only supports LBA\n");
666 if (cmdReg
.sec_count
== 0)
667 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
669 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
671 curSector
= getLBABase();
673 /** @todo make this a scheduled event to simulate disk delay */
674 devState
= Prepare_Data_In
;
675 action
= ACT_DATA_READY
;
678 // Supported PIO data-out commands
681 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
682 panic("Attempt to perform CHS access, only supports LBA\n");
684 if (cmdReg
.sec_count
== 0)
685 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
687 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
689 curSector
= getLBABase();
691 devState
= Prepare_Data_Out
;
692 action
= ACT_DATA_READY
;
695 // Supported DMA commands
697 dmaRead
= true; // a write to the disk is a DMA read from memory
699 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
700 panic("Attempt to perform CHS access, only supports LBA\n");
702 if (cmdReg
.sec_count
== 0)
703 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
705 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
707 curSector
= getLBABase();
709 devState
= Prepare_Data_Dma
;
710 action
= ACT_DMA_READY
;
714 panic("Unsupported ATA command: %#x\n", cmdReg
.command
);
717 if (action
!= ACT_NONE
) {
719 status
|= STATUS_BSY_BIT
;
721 status
&= ~STATUS_DRQ_BIT
;
723 status
&= ~STATUS_DF_BIT
;
730 // Handle setting and clearing interrupts
736 DPRINTF(IdeDisk
, "Posting Interrupt\n");
738 panic("Attempt to post an interrupt with one pending\n");
742 // talk to controller to set interrupt
750 DPRINTF(IdeDisk
, "Clearing Interrupt\n");
752 panic("Attempt to clear a non-pending interrupt\n");
756 // talk to controller to clear interrupt
762 // Manage the device internal state machine
766 IdeDisk::updateState(DevAction_t action
)
770 if (action
== ACT_SRST_SET
) {
772 status
|= STATUS_BSY_BIT
;
773 } else if (action
== ACT_SRST_CLEAR
) {
775 status
&= ~STATUS_BSY_BIT
;
777 // reset the device state
783 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
784 devState
= Device_Idle_NS
;
785 } else if (action
== ACT_CMD_WRITE
) {
792 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
793 devState
= Device_Idle_NS
;
795 } else if (action
== ACT_STAT_READ
|| isIENSet()) {
796 devState
= Device_Idle_S
;
798 } else if (action
== ACT_CMD_WRITE
) {
806 if (action
== ACT_SELECT_WRITE
&& isDEVSelect()) {
807 if (!isIENSet() && intrPending
) {
808 devState
= Device_Idle_SI
;
811 if (isIENSet() || !intrPending
) {
812 devState
= Device_Idle_S
;
817 case Command_Execution
:
818 if (action
== ACT_CMD_COMPLETE
) {
823 devState
= Device_Idle_SI
;
826 devState
= Device_Idle_S
;
831 case Prepare_Data_In
:
832 if (action
== ACT_CMD_ERROR
) {
837 devState
= Device_Idle_SI
;
840 devState
= Device_Idle_S
;
842 } else if (action
== ACT_DATA_READY
) {
844 status
&= ~STATUS_BSY_BIT
;
846 status
|= STATUS_DRQ_BIT
;
848 // copy the data into the data buffer
849 if (cmdReg
.command
== WIN_IDENTIFY
) {
850 // Reset the drqBytes for this block
851 drqBytesLeft
= sizeof(struct hd_driveid
);
853 memcpy((void *)dataBuffer
, (void *)&driveID
,
854 sizeof(struct hd_driveid
));
856 // Reset the drqBytes for this block
857 drqBytesLeft
= SectorSize
;
859 readDisk(curSector
++, dataBuffer
);
862 // put the first two bytes into the data register
863 memcpy((void *)&cmdReg
.data0
, (void *)dataBuffer
,
867 devState
= Data_Ready_INTRQ_In
;
870 devState
= Transfer_Data_In
;
875 case Data_Ready_INTRQ_In
:
876 if (action
== ACT_STAT_READ
) {
877 devState
= Transfer_Data_In
;
882 case Transfer_Data_In
:
883 if (action
== ACT_DATA_READ_BYTE
|| action
== ACT_DATA_READ_SHORT
) {
884 if (action
== ACT_DATA_READ_BYTE
) {
885 panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
890 // copy next short into data registers
892 memcpy((void *)&cmdReg
.data0
,
893 (void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
897 if (drqBytesLeft
== 0) {
898 if (cmdBytesLeft
== 0) {
901 devState
= Device_Idle_S
;
903 devState
= Prepare_Data_In
;
905 status
|= STATUS_BSY_BIT
;
907 status
&= ~STATUS_DRQ_BIT
;
909 /** @todo change this to a scheduled event to simulate
911 updateState(ACT_DATA_READY
);
917 case Prepare_Data_Out
:
918 if (action
== ACT_CMD_ERROR
|| cmdBytesLeft
== 0) {
923 devState
= Device_Idle_SI
;
926 devState
= Device_Idle_S
;
928 } else if (action
== ACT_DATA_READY
&& cmdBytesLeft
!= 0) {
930 status
&= ~STATUS_BSY_BIT
;
932 status
|= STATUS_DRQ_BIT
;
934 // clear the data buffer to get it ready for writes
935 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
937 // reset the drqBytes for this block
938 drqBytesLeft
= SectorSize
;
940 if (cmdBytesLeft
== cmdBytes
|| isIENSet()) {
941 devState
= Transfer_Data_Out
;
943 devState
= Data_Ready_INTRQ_Out
;
949 case Data_Ready_INTRQ_Out
:
950 if (action
== ACT_STAT_READ
) {
951 devState
= Transfer_Data_Out
;
956 case Transfer_Data_Out
:
957 if (action
== ACT_DATA_WRITE_BYTE
||
958 action
== ACT_DATA_WRITE_SHORT
) {
960 if (action
== ACT_DATA_READ_BYTE
) {
961 panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
963 // copy the latest short into the data buffer
964 memcpy((void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
965 (void *)&cmdReg
.data0
,
972 if (drqBytesLeft
== 0) {
973 // copy the block to the disk
974 writeDisk(curSector
++, dataBuffer
);
977 status
|= STATUS_BSY_BIT
;
979 status
|= STATUS_SEEK_BIT
;
981 status
&= ~STATUS_DRQ_BIT
;
983 devState
= Prepare_Data_Out
;
985 /** @todo change this to a scheduled event to simulate
987 updateState(ACT_DATA_READY
);
992 case Prepare_Data_Dma
:
993 if (action
== ACT_CMD_ERROR
) {
998 devState
= Device_Idle_SI
;
1001 devState
= Device_Idle_S
;
1003 } else if (action
== ACT_DMA_READY
) {
1004 // clear the BSY bit
1005 status
&= ~STATUS_BSY_BIT
;
1007 status
|= STATUS_DRQ_BIT
;
1009 devState
= Transfer_Data_Dma
;
1011 if (dmaState
!= Dma_Idle
)
1012 panic("Inconsistent DMA state, should be Dma_Idle\n");
1014 dmaState
= Dma_Start
;
1015 // wait for the write to the DMA start bit
1019 case Transfer_Data_Dma
:
1020 if (action
== ACT_CMD_ERROR
|| action
== ACT_DMA_DONE
) {
1021 // clear the BSY bit
1024 status
|= STATUS_SEEK_BIT
;
1025 // clear the controller state for DMA transfer
1026 ctrl
->setDmaComplete(this);
1029 devState
= Device_Idle_SI
;
1032 devState
= Device_Idle_S
;
1038 panic("Unknown IDE device state: %#x\n", devState
);
1043 IdeDisk::serialize(ostream
&os
)
1045 // Check all outstanding events to see if they are scheduled
1046 // these are all mutually exclusive
1047 Tick reschedule
= 0;
1048 Events_t event
= None
;
1052 if (dmaTransferEvent
.scheduled()) {
1053 reschedule
= dmaTransferEvent
.when();
1057 if (dmaReadWaitEvent
.scheduled()) {
1058 reschedule
= dmaReadWaitEvent
.when();
1062 if (dmaWriteWaitEvent
.scheduled()) {
1063 reschedule
= dmaWriteWaitEvent
.when();
1067 if (dmaPrdReadEvent
.scheduled()) {
1068 reschedule
= dmaPrdReadEvent
.when();
1072 if (dmaReadEvent
.scheduled()) {
1073 reschedule
= dmaReadEvent
.when();
1077 if (dmaWriteEvent
.scheduled()) {
1078 reschedule
= dmaWriteEvent
.when();
1083 assert(eventCount
<= 1);
1085 SERIALIZE_SCALAR(reschedule
);
1086 SERIALIZE_ENUM(event
);
1088 // Serialize device registers
1089 SERIALIZE_SCALAR(cmdReg
.data0
);
1090 SERIALIZE_SCALAR(cmdReg
.data1
);
1091 SERIALIZE_SCALAR(cmdReg
.sec_count
);
1092 SERIALIZE_SCALAR(cmdReg
.sec_num
);
1093 SERIALIZE_SCALAR(cmdReg
.cyl_low
);
1094 SERIALIZE_SCALAR(cmdReg
.cyl_high
);
1095 SERIALIZE_SCALAR(cmdReg
.drive
);
1096 SERIALIZE_SCALAR(cmdReg
.command
);
1097 SERIALIZE_SCALAR(status
);
1098 SERIALIZE_SCALAR(nIENBit
);
1099 SERIALIZE_SCALAR(devID
);
1101 // Serialize the PRD related information
1102 SERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1103 SERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1104 SERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1105 SERIALIZE_SCALAR(curPrdAddr
);
1107 // Serialize current transfer related information
1108 SERIALIZE_SCALAR(cmdBytesLeft
);
1109 SERIALIZE_SCALAR(cmdBytes
);
1110 SERIALIZE_SCALAR(drqBytesLeft
);
1111 SERIALIZE_SCALAR(curSector
);
1112 SERIALIZE_SCALAR(dmaRead
);
1113 SERIALIZE_SCALAR(dmaInterfaceBytes
);
1114 SERIALIZE_SCALAR(intrPending
);
1115 SERIALIZE_ENUM(devState
);
1116 SERIALIZE_ENUM(dmaState
);
1117 SERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1121 IdeDisk::unserialize(Checkpoint
*cp
, const string
§ion
)
1123 // Reschedule events that were outstanding
1124 // these are all mutually exclusive
1125 Tick reschedule
= 0;
1126 Events_t event
= None
;
1128 UNSERIALIZE_SCALAR(reschedule
);
1129 UNSERIALIZE_ENUM(event
);
1133 case Transfer
: dmaTransferEvent
.schedule(reschedule
); break;
1134 case ReadWait
: dmaReadWaitEvent
.schedule(reschedule
); break;
1135 case WriteWait
: dmaWriteWaitEvent
.schedule(reschedule
); break;
1136 case PrdRead
: dmaPrdReadEvent
.schedule(reschedule
); break;
1137 case DmaRead
: dmaReadEvent
.schedule(reschedule
); break;
1138 case DmaWrite
: dmaWriteEvent
.schedule(reschedule
); break;
1141 // Unserialize device registers
1142 UNSERIALIZE_SCALAR(cmdReg
.data0
);
1143 UNSERIALIZE_SCALAR(cmdReg
.data1
);
1144 UNSERIALIZE_SCALAR(cmdReg
.sec_count
);
1145 UNSERIALIZE_SCALAR(cmdReg
.sec_num
);
1146 UNSERIALIZE_SCALAR(cmdReg
.cyl_low
);
1147 UNSERIALIZE_SCALAR(cmdReg
.cyl_high
);
1148 UNSERIALIZE_SCALAR(cmdReg
.drive
);
1149 UNSERIALIZE_SCALAR(cmdReg
.command
);
1150 UNSERIALIZE_SCALAR(status
);
1151 UNSERIALIZE_SCALAR(nIENBit
);
1152 UNSERIALIZE_SCALAR(devID
);
1154 // Unserialize the PRD related information
1155 UNSERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1156 UNSERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1157 UNSERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1158 UNSERIALIZE_SCALAR(curPrdAddr
);
1160 // Unserialize current transfer related information
1161 UNSERIALIZE_SCALAR(cmdBytes
);
1162 UNSERIALIZE_SCALAR(cmdBytesLeft
);
1163 UNSERIALIZE_SCALAR(drqBytesLeft
);
1164 UNSERIALIZE_SCALAR(curSector
);
1165 UNSERIALIZE_SCALAR(dmaRead
);
1166 UNSERIALIZE_SCALAR(dmaInterfaceBytes
);
1167 UNSERIALIZE_SCALAR(intrPending
);
1168 UNSERIALIZE_ENUM(devState
);
1169 UNSERIALIZE_ENUM(dmaState
);
1170 UNSERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1173 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1175 enum DriveID
{ master
, slave
};
1176 static const char *DriveID_strings
[] = { "master", "slave" };
1177 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk
)
1179 SimObjectParam
<DiskImage
*> image
;
1180 SimObjectParam
<PhysicalMemory
*> physmem
;
1181 SimpleEnumParam
<DriveID
> driveID
;
1184 END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk
)
1186 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk
)
1188 INIT_PARAM(image
, "Disk image"),
1189 INIT_PARAM(physmem
, "Physical memory"),
1190 INIT_ENUM_PARAM(driveID
, "Drive ID (0=master 1=slave)", DriveID_strings
),
1191 INIT_PARAM_DFLT(delay
, "Fixed disk delay in microseconds", 1)
1193 END_INIT_SIM_OBJECT_PARAMS(IdeDisk
)
1196 CREATE_SIM_OBJECT(IdeDisk
)
1198 return new IdeDisk(getInstanceName(), image
, physmem
, driveID
, delay
);
1201 REGISTER_SIM_OBJECT("IdeDisk", IdeDisk
)
1203 #endif //DOXYGEN_SHOULD_SKIP_THIS