f3760bd5efa67924125dfc266cf53b9d5dd230f6
2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Device model implementation for an IDE disk
38 #include "base/cprintf.hh" // csprintf
39 #include "base/trace.hh"
40 #include "dev/disk_image.hh"
41 #include "dev/ide_disk.hh"
42 #include "dev/ide_ctrl.hh"
43 #include "dev/tsunami.hh"
44 #include "dev/tsunami_pchip.hh"
45 #include "mem/functional_mem/physical_memory.hh"
46 #include "mem/bus/bus.hh"
47 #include "mem/bus/dma_interface.hh"
48 #include "mem/bus/pio_interface.hh"
49 #include "mem/bus/pio_interface_impl.hh"
50 #include "sim/builder.hh"
51 #include "sim/sim_object.hh"
52 #include "sim/universe.hh"
53 #include "targetarch/isa_traits.hh"
57 IdeDisk::IdeDisk(const string
&name
, DiskImage
*img
, PhysicalMemory
*phys
,
59 : SimObject(name
), ctrl(NULL
), image(img
), physmem(phys
),
60 dmaTransferEvent(this), dmaReadWaitEvent(this),
61 dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
62 dmaReadEvent(this), dmaWriteEvent(this)
64 // Reset the device state
67 // calculate disk delay in microseconds
68 diskDelay
= (delay
* ticksPerSecond
/ 100000);
70 // fill out the drive ID structure
71 memset(&driveID
, 0, sizeof(struct hd_driveid
));
73 // Calculate LBA and C/H/S values
78 uint32_t lba_size
= image
->size();
79 if (lba_size
>= 16383*16*63) {
89 if ((lba_size
/ sectors
) >= 16)
92 heads
= (lba_size
/ sectors
);
94 cylinders
= lba_size
/ (heads
* sectors
);
97 // Setup the model name
98 sprintf((char *)driveID
.model
, "5MI EDD si k");
99 // Set the maximum multisector transfer size
100 driveID
.max_multsect
= MAX_MULTSECT
;
101 // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
102 driveID
.capability
= 0x7;
103 // UDMA support, EIDE support
104 driveID
.field_valid
= 0x6;
105 // Setup default C/H/S settings
106 driveID
.cyls
= cylinders
;
107 driveID
.sectors
= sectors
;
108 driveID
.heads
= heads
;
109 // Setup the current multisector transfer size
110 driveID
.multsect
= MAX_MULTSECT
;
111 driveID
.multsect_valid
= 0x1;
112 // Number of sectors on disk
113 driveID
.lba_capacity
= lba_size
;
114 // Multiword DMA mode 2 and below supported
115 driveID
.dma_mword
= 0x400;
116 // Set PIO mode 4 and 3 supported
117 driveID
.eide_pio_modes
= 0x3;
118 // Set DMA mode 4 and below supported
119 driveID
.dma_ultra
= 0x10;
120 // Statically set hardware config word
121 driveID
.hw_config
= 0x4001;
126 // destroy the data buffer
127 delete [] dataBuffer
;
131 IdeDisk::reset(int id
)
133 // initialize the data buffer and shadow registers
134 dataBuffer
= new uint8_t[MAX_DMA_SIZE
];
136 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
137 memset(&cmdReg
, 0, sizeof(CommandReg_t
));
138 memset(&curPrd
.entry
, 0, sizeof(PrdEntry_t
));
140 dmaInterfaceBytes
= 0;
149 // set the device state to idle
153 devState
= Device_Idle_S
;
155 } else if (id
== DEV1
) {
156 devState
= Device_Idle_NS
;
159 panic("Invalid device ID: %#x\n", id
);
162 // set the device ready bit
163 status
= STATUS_DRDY_BIT
;
171 IdeDisk::isDEVSelect()
173 return ctrl
->isDiskSelected(this);
177 IdeDisk::pciToDma(Addr pciAddr
)
180 return ctrl
->tsunami
->pchip
->translatePciToDma(pciAddr
);
182 panic("Access to unset controller!\n");
186 IdeDisk::bytesInDmaPage(Addr curAddr
, uint32_t bytesLeft
)
188 uint32_t bytesInPage
= 0;
190 // First calculate how many bytes could be in the page
191 if (bytesLeft
> TheISA::PageBytes
)
192 bytesInPage
= TheISA::PageBytes
;
194 bytesInPage
= bytesLeft
;
196 // Next, see if we have crossed a page boundary, and adjust
197 Addr upperBound
= curAddr
+ bytesInPage
;
198 Addr pageBound
= TheISA::TruncPage(curAddr
) + TheISA::PageBytes
;
200 assert(upperBound
>= curAddr
&& "DMA read wraps around address space!\n");
202 if (upperBound
>= pageBound
)
203 bytesInPage
= pageBound
- curAddr
;
209 // Device registers read/write
213 IdeDisk::read(const Addr
&offset
, bool byte
, bool cmdBlk
, uint8_t *data
)
215 DevAction_t action
= ACT_NONE
;
218 if (offset
< 0 || offset
> sizeof(CommandReg_t
))
219 panic("Invalid disk command register offset: %#x\n", offset
);
221 if (!byte
&& offset
!= DATA_OFFSET
)
222 panic("Invalid 16-bit read, only allowed on data reg\n");
225 *(uint16_t *)data
= *(uint16_t *)&cmdReg
.data0
;
227 *data
= ((uint8_t *)&cmdReg
)[offset
];
229 // determine if an action needs to be taken on the state machine
230 if (offset
== STATUS_OFFSET
) {
231 action
= ACT_STAT_READ
;
232 *data
= status
; // status is in a shadow, explicity copy
233 } else if (offset
== DATA_OFFSET
) {
235 action
= ACT_DATA_READ_BYTE
;
237 action
= ACT_DATA_READ_SHORT
;
241 if (offset
!= ALTSTAT_OFFSET
)
242 panic("Invalid disk control register offset: %#x\n", offset
);
245 panic("Invalid 16-bit read from control block\n");
250 if (action
!= ACT_NONE
)
255 IdeDisk::write(const Addr
&offset
, bool byte
, bool cmdBlk
, const uint8_t *data
)
257 DevAction_t action
= ACT_NONE
;
260 if (offset
< 0 || offset
> sizeof(CommandReg_t
))
261 panic("Invalid disk command register offset: %#x\n", offset
);
263 if (!byte
&& offset
!= DATA_OFFSET
)
264 panic("Invalid 16-bit write, only allowed on data reg\n");
267 *((uint16_t *)&cmdReg
.data0
) = *(uint16_t *)data
;
269 ((uint8_t *)&cmdReg
)[offset
] = *data
;
271 // determine if an action needs to be taken on the state machine
272 if (offset
== COMMAND_OFFSET
) {
273 action
= ACT_CMD_WRITE
;
274 } else if (offset
== DATA_OFFSET
) {
276 action
= ACT_DATA_WRITE_BYTE
;
278 action
= ACT_DATA_WRITE_SHORT
;
279 } else if (offset
== SELECT_OFFSET
) {
280 action
= ACT_SELECT_WRITE
;
284 if (offset
!= CONTROL_OFFSET
)
285 panic("Invalid disk control register offset: %#x\n", offset
);
288 panic("Invalid 16-bit write to control block\n");
290 if (*data
& CONTROL_RST_BIT
) {
291 // force the device into the reset state
292 devState
= Device_Srst
;
293 action
= ACT_SRST_SET
;
294 } else if (devState
== Device_Srst
&& !(*data
& CONTROL_RST_BIT
)) {
295 action
= ACT_SRST_CLEAR
;
298 nIENBit
= (*data
& CONTROL_IEN_BIT
) ? true : false;
301 if (action
!= ACT_NONE
)
306 // Perform DMA transactions
310 IdeDisk::doDmaTransfer()
312 if (dmaState
!= Dma_Transfer
|| devState
!= Transfer_Data_Dma
)
313 panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
316 // first read the current PRD
318 if (dmaInterface
->busy()) {
319 // reschedule after waiting period
320 dmaTransferEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
324 dmaInterface
->doDMA(Read
, curPrdAddr
, sizeof(PrdEntry_t
), curTick
,
332 IdeDisk::dmaPrdReadDone()
334 // actually copy the PRD from physical memory
335 memcpy((void *)&curPrd
.entry
,
336 physmem
->dma_addr(curPrdAddr
, sizeof(PrdEntry_t
)),
339 DPRINTF(IdeDisk
, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
340 curPrd
.getBaseAddr(), pciToDma(curPrd
.getBaseAddr()),
341 curPrd
.getByteCount(), (cmdBytesLeft
/SectorSize
),
342 curPrd
.getEOT(), curSector
);
344 // the prd pointer has already been translated, so just do an increment
345 curPrdAddr
= curPrdAddr
+ sizeof(PrdEntry_t
);
356 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
359 if (dmaInterface
->busy()) {
360 // reschedule after waiting period
361 dmaReadWaitEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
365 Addr dmaAddr
= pciToDma(curPrd
.getBaseAddr());
367 uint32_t bytesInPage
= bytesInDmaPage(curPrd
.getBaseAddr(),
368 (uint32_t)curPrd
.getByteCount());
370 dmaInterfaceBytes
= bytesInPage
;
372 dmaInterface
->doDMA(Read
, dmaAddr
, bytesInPage
,
373 curTick
+ totalDiskDelay
, &dmaReadEvent
);
375 // schedule dmaReadEvent with sectorDelay (dmaReadDone)
376 dmaReadEvent
.schedule(curTick
+ totalDiskDelay
);
381 IdeDisk::dmaReadDone()
384 Addr curAddr
= 0, dmaAddr
= 0;
385 uint32_t bytesWritten
= 0, bytesInPage
= 0, bytesLeft
= 0;
387 // continue to use the DMA interface until all pages are read
388 if (dmaInterface
&& (dmaInterfaceBytes
< curPrd
.getByteCount())) {
389 // see if the interface is busy
390 if (dmaInterface
->busy()) {
391 // reschedule after waiting period
392 dmaReadEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
396 uint32_t bytesLeft
= curPrd
.getByteCount() - dmaInterfaceBytes
;
397 curAddr
= curPrd
.getBaseAddr() + dmaInterfaceBytes
;
398 dmaAddr
= pciToDma(curAddr
);
400 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
401 dmaInterfaceBytes
+= bytesInPage
;
403 dmaInterface
->doDMA(Read
, dmaAddr
, bytesInPage
,
404 curTick
, &dmaReadEvent
);
409 // set initial address
410 curAddr
= curPrd
.getBaseAddr();
412 // clear out the data buffer
413 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
415 // read the data from memory via DMA into a data buffer
416 while (bytesWritten
< curPrd
.getByteCount()) {
417 if (cmdBytesLeft
<= 0)
418 panic("DMA data is larger than # of sectors specified\n");
420 dmaAddr
= pciToDma(curAddr
);
422 // calculate how many bytes are in the current page
423 bytesLeft
= curPrd
.getByteCount() - bytesWritten
;
424 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
426 // copy the data from memory into the data buffer
427 memcpy((void *)(dataBuffer
+ bytesWritten
),
428 physmem
->dma_addr(dmaAddr
, bytesInPage
),
431 curAddr
+= bytesInPage
;
432 bytesWritten
+= bytesInPage
;
433 cmdBytesLeft
-= bytesInPage
;
436 // write the data to the disk image
437 for (bytesWritten
= 0;
438 bytesWritten
< curPrd
.getByteCount();
439 bytesWritten
+= SectorSize
) {
441 writeDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesWritten
));
445 if (curPrd
.getEOT()) {
446 assert(cmdBytesLeft
== 0);
448 updateState(ACT_DMA_DONE
);
455 IdeDisk::doDmaWrite()
457 Tick totalDiskDelay
= diskDelay
+ (curPrd
.getByteCount() / SectorSize
);
460 if (dmaInterface
->busy()) {
461 // reschedule after waiting period
462 dmaWriteWaitEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
466 Addr dmaAddr
= pciToDma(curPrd
.getBaseAddr());
468 uint32_t bytesInPage
= bytesInDmaPage(curPrd
.getBaseAddr(),
469 (uint32_t)curPrd
.getByteCount());
471 dmaInterfaceBytes
= bytesInPage
;
473 dmaInterface
->doDMA(WriteInvalidate
, dmaAddr
,
474 bytesInPage
, curTick
+ totalDiskDelay
,
477 // schedule event with disk delay (dmaWriteDone)
478 dmaWriteEvent
.schedule(curTick
+ totalDiskDelay
);
483 IdeDisk::dmaWriteDone()
485 Addr curAddr
= 0, pageAddr
= 0, dmaAddr
= 0;
486 uint32_t bytesRead
= 0, bytesInPage
= 0;
488 // continue to use the DMA interface until all pages are read
489 if (dmaInterface
&& (dmaInterfaceBytes
< curPrd
.getByteCount())) {
490 // see if the interface is busy
491 if (dmaInterface
->busy()) {
492 // reschedule after waiting period
493 dmaWriteEvent
.schedule(curTick
+ DMA_BACKOFF_PERIOD
);
497 uint32_t bytesLeft
= curPrd
.getByteCount() - dmaInterfaceBytes
;
498 curAddr
= curPrd
.getBaseAddr() + dmaInterfaceBytes
;
499 dmaAddr
= pciToDma(curAddr
);
501 bytesInPage
= bytesInDmaPage(curAddr
, bytesLeft
);
502 dmaInterfaceBytes
+= bytesInPage
;
504 dmaInterface
->doDMA(WriteInvalidate
, dmaAddr
,
505 bytesInPage
, curTick
,
511 // setup the initial page and DMA address
512 curAddr
= curPrd
.getBaseAddr();
513 pageAddr
= TheISA::TruncPage(curAddr
);
514 dmaAddr
= pciToDma(curAddr
);
516 // clear out the data buffer
517 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
519 while (bytesRead
< curPrd
.getByteCount()) {
520 // see if we have crossed into a new page
521 if (pageAddr
!= TheISA::TruncPage(curAddr
)) {
522 // write the data to memory
523 memcpy(physmem
->dma_addr(dmaAddr
, bytesInPage
),
524 (void *)(dataBuffer
+ (bytesRead
- bytesInPage
)),
527 // update the DMA address and page address
528 pageAddr
= TheISA::TruncPage(curAddr
);
529 dmaAddr
= pciToDma(curAddr
);
534 if (cmdBytesLeft
<= 0)
535 panic("DMA requested data is larger than # sectors specified\n");
537 readDisk(curSector
++, (uint8_t *)(dataBuffer
+ bytesRead
));
539 curAddr
+= SectorSize
;
540 bytesRead
+= SectorSize
;
541 bytesInPage
+= SectorSize
;
542 cmdBytesLeft
-= SectorSize
;
545 // write the last page worth read to memory
546 if (bytesInPage
!= 0) {
547 memcpy(physmem
->dma_addr(dmaAddr
, bytesInPage
),
548 (void *)(dataBuffer
+ (bytesRead
- bytesInPage
)),
553 if (curPrd
.getEOT()) {
554 assert(cmdBytesLeft
== 0);
556 updateState(ACT_DMA_DONE
);
563 // Disk utility routines
567 IdeDisk::readDisk(uint32_t sector
, uint8_t *data
)
569 uint32_t bytesRead
= image
->read(data
, sector
);
571 if (bytesRead
!= SectorSize
)
572 panic("Can't read from %s. Only %d of %d read. errno=%d\n",
573 name(), bytesRead
, SectorSize
, errno
);
577 IdeDisk::writeDisk(uint32_t sector
, uint8_t *data
)
579 uint32_t bytesWritten
= image
->write(data
, sector
);
581 if (bytesWritten
!= SectorSize
)
582 panic("Can't write to %s. Only %d of %d written. errno=%d\n",
583 name(), bytesWritten
, SectorSize
, errno
);
587 // Setup and handle commands
591 IdeDisk::startDma(const uint32_t &prdTableBase
)
593 if (dmaState
!= Dma_Start
)
594 panic("Inconsistent DMA state, should be in Dma_Start!\n");
596 if (devState
!= Transfer_Data_Dma
)
597 panic("Inconsistent device state for DMA start!\n");
599 // PRD base address is given by bits 31:2
600 curPrdAddr
= pciToDma((Addr
)(prdTableBase
& ~ULL(0x3)));
602 dmaState
= Dma_Transfer
;
604 // schedule dma transfer (doDmaTransfer)
605 dmaTransferEvent
.schedule(curTick
+ 1);
611 if (dmaState
== Dma_Idle
)
612 panic("Inconsistent DMA state, should be in Dma_Start or Dma_Transfer!\n");
614 if (devState
!= Transfer_Data_Dma
&& devState
!= Prepare_Data_Dma
)
615 panic("Inconsistent device state, should be in Transfer or Prepare!\n");
617 updateState(ACT_CMD_ERROR
);
621 IdeDisk::startCommand()
623 DevAction_t action
= ACT_NONE
;
628 switch (cmdReg
.command
) {
629 // Supported non-data commands
630 case WIN_READ_NATIVE_MAX
:
631 size
= image
->size() - 1;
632 cmdReg
.sec_num
= (size
& 0xff);
633 cmdReg
.cyl_low
= ((size
& 0xff00) >> 8);
634 cmdReg
.cyl_high
= ((size
& 0xff0000) >> 16);
635 cmdReg
.head
= ((size
& 0xf000000) >> 24);
637 devState
= Command_Execution
;
638 action
= ACT_CMD_COMPLETE
;
643 case WIN_STANDBYNOW1
:
644 case WIN_FLUSH_CACHE
:
647 case WIN_SETFEATURES
:
649 devState
= Command_Execution
;
650 action
= ACT_CMD_COMPLETE
;
653 // Supported PIO data-in commands
655 cmdBytes
= cmdBytesLeft
= sizeof(struct hd_driveid
);
656 devState
= Prepare_Data_In
;
657 action
= ACT_DATA_READY
;
662 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
663 panic("Attempt to perform CHS access, only supports LBA\n");
665 if (cmdReg
.sec_count
== 0)
666 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
668 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
670 curSector
= getLBABase();
672 /** @todo make this a scheduled event to simulate disk delay */
673 devState
= Prepare_Data_In
;
674 action
= ACT_DATA_READY
;
677 // Supported PIO data-out commands
680 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
681 panic("Attempt to perform CHS access, only supports LBA\n");
683 if (cmdReg
.sec_count
== 0)
684 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
686 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
688 curSector
= getLBABase();
690 devState
= Prepare_Data_Out
;
691 action
= ACT_DATA_READY
;
694 // Supported DMA commands
696 dmaRead
= true; // a write to the disk is a DMA read from memory
698 if (!(cmdReg
.drive
& DRIVE_LBA_BIT
))
699 panic("Attempt to perform CHS access, only supports LBA\n");
701 if (cmdReg
.sec_count
== 0)
702 cmdBytes
= cmdBytesLeft
= (256 * SectorSize
);
704 cmdBytes
= cmdBytesLeft
= (cmdReg
.sec_count
* SectorSize
);
706 curSector
= getLBABase();
708 devState
= Prepare_Data_Dma
;
709 action
= ACT_DMA_READY
;
713 panic("Unsupported ATA command: %#x\n", cmdReg
.command
);
716 if (action
!= ACT_NONE
) {
718 status
|= STATUS_BSY_BIT
;
720 status
&= ~STATUS_DRQ_BIT
;
722 status
&= ~STATUS_DF_BIT
;
729 // Handle setting and clearing interrupts
735 DPRINTF(IdeDisk
, "IDE Disk Posting Interrupt\n");
737 panic("Attempt to post an interrupt with one pending\n");
741 // talk to controller to set interrupt
749 DPRINTF(IdeDisk
, "IDE Disk Clearing Interrupt\n");
751 panic("Attempt to clear a non-pending interrupt\n");
755 // talk to controller to clear interrupt
761 // Manage the device internal state machine
765 IdeDisk::updateState(DevAction_t action
)
769 if (action
== ACT_SRST_SET
) {
771 status
|= STATUS_BSY_BIT
;
772 } else if (action
== ACT_SRST_CLEAR
) {
774 status
&= ~STATUS_BSY_BIT
;
776 // reset the device state
782 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
783 devState
= Device_Idle_NS
;
784 } else if (action
== ACT_CMD_WRITE
) {
791 if (action
== ACT_SELECT_WRITE
&& !isDEVSelect()) {
792 devState
= Device_Idle_NS
;
794 } else if (action
== ACT_STAT_READ
|| isIENSet()) {
795 devState
= Device_Idle_S
;
797 } else if (action
== ACT_CMD_WRITE
) {
805 if (action
== ACT_SELECT_WRITE
&& isDEVSelect()) {
806 if (!isIENSet() && intrPending
) {
807 devState
= Device_Idle_SI
;
810 if (isIENSet() || !intrPending
) {
811 devState
= Device_Idle_S
;
816 case Command_Execution
:
817 if (action
== ACT_CMD_COMPLETE
) {
822 devState
= Device_Idle_SI
;
825 devState
= Device_Idle_S
;
830 case Prepare_Data_In
:
831 if (action
== ACT_CMD_ERROR
) {
836 devState
= Device_Idle_SI
;
839 devState
= Device_Idle_S
;
841 } else if (action
== ACT_DATA_READY
) {
843 status
&= ~STATUS_BSY_BIT
;
845 status
|= STATUS_DRQ_BIT
;
847 // copy the data into the data buffer
848 if (cmdReg
.command
== WIN_IDENTIFY
) {
849 // Reset the drqBytes for this block
850 drqBytesLeft
= sizeof(struct hd_driveid
);
852 memcpy((void *)dataBuffer
, (void *)&driveID
,
853 sizeof(struct hd_driveid
));
855 // Reset the drqBytes for this block
856 drqBytesLeft
= SectorSize
;
858 readDisk(curSector
++, dataBuffer
);
861 // put the first two bytes into the data register
862 memcpy((void *)&cmdReg
.data0
, (void *)dataBuffer
,
866 devState
= Data_Ready_INTRQ_In
;
869 devState
= Transfer_Data_In
;
874 case Data_Ready_INTRQ_In
:
875 if (action
== ACT_STAT_READ
) {
876 devState
= Transfer_Data_In
;
881 case Transfer_Data_In
:
882 if (action
== ACT_DATA_READ_BYTE
|| action
== ACT_DATA_READ_SHORT
) {
883 if (action
== ACT_DATA_READ_BYTE
) {
884 panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
889 // copy next short into data registers
891 memcpy((void *)&cmdReg
.data0
,
892 (void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
896 if (drqBytesLeft
== 0) {
897 if (cmdBytesLeft
== 0) {
900 devState
= Device_Idle_S
;
902 devState
= Prepare_Data_In
;
904 status
|= STATUS_BSY_BIT
;
906 status
&= ~STATUS_DRQ_BIT
;
908 /** @todo change this to a scheduled event to simulate
910 updateState(ACT_DATA_READY
);
916 case Prepare_Data_Out
:
917 if (action
== ACT_CMD_ERROR
|| cmdBytesLeft
== 0) {
922 devState
= Device_Idle_SI
;
925 devState
= Device_Idle_S
;
927 } else if (action
== ACT_DATA_READY
&& cmdBytesLeft
!= 0) {
929 status
&= ~STATUS_BSY_BIT
;
931 status
|= STATUS_DRQ_BIT
;
933 // clear the data buffer to get it ready for writes
934 memset(dataBuffer
, 0, MAX_DMA_SIZE
);
936 // reset the drqBytes for this block
937 drqBytesLeft
= SectorSize
;
939 if (cmdBytesLeft
== cmdBytes
|| isIENSet()) {
940 devState
= Transfer_Data_Out
;
942 devState
= Data_Ready_INTRQ_Out
;
948 case Data_Ready_INTRQ_Out
:
949 if (action
== ACT_STAT_READ
) {
950 devState
= Transfer_Data_Out
;
955 case Transfer_Data_Out
:
956 if (action
== ACT_DATA_WRITE_BYTE
||
957 action
== ACT_DATA_WRITE_SHORT
) {
959 if (action
== ACT_DATA_READ_BYTE
) {
960 panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
962 // copy the latest short into the data buffer
963 memcpy((void *)&dataBuffer
[SectorSize
- drqBytesLeft
],
964 (void *)&cmdReg
.data0
,
971 if (drqBytesLeft
== 0) {
972 // copy the block to the disk
973 writeDisk(curSector
++, dataBuffer
);
976 status
|= STATUS_BSY_BIT
;
978 status
|= STATUS_SEEK_BIT
;
980 status
&= ~STATUS_DRQ_BIT
;
982 devState
= Prepare_Data_Out
;
984 /** @todo change this to a scheduled event to simulate
986 updateState(ACT_DATA_READY
);
991 case Prepare_Data_Dma
:
992 if (action
== ACT_CMD_ERROR
) {
997 devState
= Device_Idle_SI
;
1000 devState
= Device_Idle_S
;
1002 } else if (action
== ACT_DMA_READY
) {
1003 // clear the BSY bit
1004 status
&= ~STATUS_BSY_BIT
;
1006 status
|= STATUS_DRQ_BIT
;
1008 devState
= Transfer_Data_Dma
;
1010 if (dmaState
!= Dma_Idle
)
1011 panic("Inconsistent DMA state, should be Dma_Idle\n");
1013 dmaState
= Dma_Start
;
1014 // wait for the write to the DMA start bit
1018 case Transfer_Data_Dma
:
1019 if (action
== ACT_CMD_ERROR
|| action
== ACT_DMA_DONE
) {
1020 // clear the BSY bit
1023 status
|= STATUS_SEEK_BIT
;
1024 // clear the controller state for DMA transfer
1025 ctrl
->setDmaComplete(this);
1028 devState
= Device_Idle_SI
;
1031 devState
= Device_Idle_S
;
1037 panic("Unknown IDE device state: %#x\n", devState
);
1042 IdeDisk::serialize(ostream
&os
)
1044 // Check all outstanding events to see if they are scheduled
1045 // these are all mutually exclusive
1046 Tick reschedule
= 0;
1047 Events_t event
= None
;
1051 if (dmaTransferEvent
.scheduled()) {
1052 reschedule
= dmaTransferEvent
.when();
1056 if (dmaReadWaitEvent
.scheduled()) {
1057 reschedule
= dmaReadWaitEvent
.when();
1061 if (dmaWriteWaitEvent
.scheduled()) {
1062 reschedule
= dmaWriteWaitEvent
.when();
1066 if (dmaPrdReadEvent
.scheduled()) {
1067 reschedule
= dmaPrdReadEvent
.when();
1071 if (dmaReadEvent
.scheduled()) {
1072 reschedule
= dmaReadEvent
.when();
1076 if (dmaWriteEvent
.scheduled()) {
1077 reschedule
= dmaWriteEvent
.when();
1082 assert(eventCount
<= 1);
1084 SERIALIZE_SCALAR(reschedule
);
1085 SERIALIZE_ENUM(event
);
1087 // Serialize device registers
1088 SERIALIZE_SCALAR(cmdReg
.data0
);
1089 SERIALIZE_SCALAR(cmdReg
.data1
);
1090 SERIALIZE_SCALAR(cmdReg
.sec_count
);
1091 SERIALIZE_SCALAR(cmdReg
.sec_num
);
1092 SERIALIZE_SCALAR(cmdReg
.cyl_low
);
1093 SERIALIZE_SCALAR(cmdReg
.cyl_high
);
1094 SERIALIZE_SCALAR(cmdReg
.drive
);
1095 SERIALIZE_SCALAR(cmdReg
.command
);
1096 SERIALIZE_SCALAR(status
);
1097 SERIALIZE_SCALAR(nIENBit
);
1098 SERIALIZE_SCALAR(devID
);
1100 // Serialize the PRD related information
1101 SERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1102 SERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1103 SERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1104 SERIALIZE_SCALAR(curPrdAddr
);
1106 // Serialize current transfer related information
1107 SERIALIZE_SCALAR(cmdBytesLeft
);
1108 SERIALIZE_SCALAR(cmdBytes
);
1109 SERIALIZE_SCALAR(drqBytesLeft
);
1110 SERIALIZE_SCALAR(curSector
);
1111 SERIALIZE_SCALAR(dmaRead
);
1112 SERIALIZE_SCALAR(dmaInterfaceBytes
);
1113 SERIALIZE_SCALAR(intrPending
);
1114 SERIALIZE_ENUM(devState
);
1115 SERIALIZE_ENUM(dmaState
);
1116 SERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1120 IdeDisk::unserialize(Checkpoint
*cp
, const string
§ion
)
1122 // Reschedule events that were outstanding
1123 // these are all mutually exclusive
1124 Tick reschedule
= 0;
1125 Events_t event
= None
;
1127 UNSERIALIZE_SCALAR(reschedule
);
1128 UNSERIALIZE_ENUM(event
);
1132 case Transfer
: dmaTransferEvent
.schedule(reschedule
); break;
1133 case ReadWait
: dmaReadWaitEvent
.schedule(reschedule
); break;
1134 case WriteWait
: dmaWriteWaitEvent
.schedule(reschedule
); break;
1135 case PrdRead
: dmaPrdReadEvent
.schedule(reschedule
); break;
1136 case DmaRead
: dmaReadEvent
.schedule(reschedule
); break;
1137 case DmaWrite
: dmaWriteEvent
.schedule(reschedule
); break;
1140 // Unserialize device registers
1141 UNSERIALIZE_SCALAR(cmdReg
.data0
);
1142 UNSERIALIZE_SCALAR(cmdReg
.data1
);
1143 UNSERIALIZE_SCALAR(cmdReg
.sec_count
);
1144 UNSERIALIZE_SCALAR(cmdReg
.sec_num
);
1145 UNSERIALIZE_SCALAR(cmdReg
.cyl_low
);
1146 UNSERIALIZE_SCALAR(cmdReg
.cyl_high
);
1147 UNSERIALIZE_SCALAR(cmdReg
.drive
);
1148 UNSERIALIZE_SCALAR(cmdReg
.command
);
1149 UNSERIALIZE_SCALAR(status
);
1150 UNSERIALIZE_SCALAR(nIENBit
);
1151 UNSERIALIZE_SCALAR(devID
);
1153 // Unserialize the PRD related information
1154 UNSERIALIZE_SCALAR(curPrd
.entry
.baseAddr
);
1155 UNSERIALIZE_SCALAR(curPrd
.entry
.byteCount
);
1156 UNSERIALIZE_SCALAR(curPrd
.entry
.endOfTable
);
1157 UNSERIALIZE_SCALAR(curPrdAddr
);
1159 // Unserialize current transfer related information
1160 UNSERIALIZE_SCALAR(cmdBytes
);
1161 UNSERIALIZE_SCALAR(cmdBytesLeft
);
1162 UNSERIALIZE_SCALAR(drqBytesLeft
);
1163 UNSERIALIZE_SCALAR(curSector
);
1164 UNSERIALIZE_SCALAR(dmaRead
);
1165 UNSERIALIZE_SCALAR(dmaInterfaceBytes
);
1166 UNSERIALIZE_SCALAR(intrPending
);
1167 UNSERIALIZE_ENUM(devState
);
1168 UNSERIALIZE_ENUM(dmaState
);
1169 UNSERIALIZE_ARRAY(dataBuffer
, MAX_DMA_SIZE
);
1172 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1174 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk
)
1176 SimObjectParam
<DiskImage
*> image
;
1177 SimObjectParam
<PhysicalMemory
*> physmem
;
1179 Param
<int> disk_delay
;
1181 END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk
)
1183 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk
)
1185 INIT_PARAM(image
, "Disk image"),
1186 INIT_PARAM(physmem
, "Physical memory"),
1187 INIT_PARAM(driveID
, "Drive ID (0=master 1=slave)"),
1188 INIT_PARAM_DFLT(disk_delay
, "Fixed disk delay in microseconds", 1)
1190 END_INIT_SIM_OBJECT_PARAMS(IdeDisk
)
1193 CREATE_SIM_OBJECT(IdeDisk
)
1195 return new IdeDisk(getInstanceName(), image
, physmem
, driveID
,
1199 REGISTER_SIM_OBJECT("IdeDisk", IdeDisk
)
1201 #endif //DOXYGEN_SHOULD_SKIP_THIS