dev/ide_disk.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Device model implementation for an IDE disk
  31  */
  32
  33 #include <cerrno>
  34 #include <cstring>
  35 #include <deque>
  36 #include <string>
  37
  38 #include "arch/alpha/pmap.h"
  39 #include "base/cprintf.hh" // csprintf
  40 #include "base/trace.hh"
  41 #include "dev/disk_image.hh"
  42 #include "dev/ide_disk.hh"
  43 #include "dev/ide_ctrl.hh"
  44 #include "dev/tsunami.hh"
  45 #include "dev/tsunami_pchip.hh"
  46 #include "mem/functional_mem/physical_memory.hh"
  47 #include "mem/bus/bus.hh"
  48 #include "mem/bus/dma_interface.hh"
  49 #include "mem/bus/pio_interface.hh"
  50 #include "mem/bus/pio_interface_impl.hh"
  51 #include "sim/builder.hh"
  52 #include "sim/sim_object.hh"
  53 #include "sim/universe.hh"
  54
  55 using namespace std;
  56
  57 IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
  58                  int id, int delay)
  59     : SimObject(name), ctrl(NULL), image(img), physmem(phys),
  60       dmaTransferEvent(this), dmaReadWaitEvent(this),
  61       dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
  62       dmaReadEvent(this), dmaWriteEvent(this)
  63 {
  64     // Reset the device state
  65     reset(id);
  66
  67     // calculate disk delay in microseconds
  68     diskDelay = (delay * ticksPerSecond / 100000);
  69
  70     // fill out the drive ID structure
  71     memset(&driveID, 0, sizeof(struct hd_driveid));
  72
  73     // Calculate LBA and C/H/S values
  74     uint16_t cylinders;
  75     uint8_t heads;
  76     uint8_t sectors;
  77
  78     uint32_t lba_size = image->size();
  79     if (lba_size >= 16383*16*63) {
  80         cylinders = 16383;
  81         heads = 16;
  82         sectors = 63;
  83     } else {
  84         if (lba_size >= 63)
  85             sectors = 63;
  86         else
  87             sectors = lba_size;
  88
  89         if ((lba_size / sectors) >= 16)
  90             heads = 16;
  91         else
  92             heads = (lba_size / sectors);
  93
  94         cylinders = lba_size / (heads * sectors);
  95     }
  96
  97     // Setup the model name
  98     sprintf((char *)driveID.model, "5MI EDD si k");
  99     // Set the maximum multisector transfer size
 100     driveID.max_multsect = MAX_MULTSECT;
 101     // IORDY supported, IORDY disabled, LBA enabled, DMA enabled
 102     driveID.capability = 0x7;
 103     // UDMA support, EIDE support
 104     driveID.field_valid = 0x6;
 105     // Setup default C/H/S settings
 106     driveID.cyls = cylinders;
 107     driveID.sectors = sectors;
 108     driveID.heads = heads;
 109     // Setup the current multisector transfer size
 110     driveID.multsect = MAX_MULTSECT;
 111     driveID.multsect_valid = 0x1;
 112     // Number of sectors on disk
 113     driveID.lba_capacity = lba_size;
 114     // Multiword DMA mode 2 and below supported
 115     driveID.dma_mword = 0x400;
 116     // Set PIO mode 4 and 3 supported
 117     driveID.eide_pio_modes = 0x3;
 118     // Set DMA mode 4 and below supported
 119     driveID.dma_ultra = 0x10;
 120     // Statically set hardware config word
 121     driveID.hw_config = 0x4001;
 122 }
 123
 124 IdeDisk::~IdeDisk()
 125 {
 126     // destroy the data buffer
 127     delete [] dataBuffer;
 128 }
 129
 130 void
 131 IdeDisk::reset(int id)
 132 {
 133     // initialize the data buffer and shadow registers
 134     dataBuffer = new uint8_t[MAX_DMA_SIZE];
 135
 136     memset(dataBuffer, 0, MAX_DMA_SIZE);
 137     memset(&cmdReg, 0, sizeof(CommandReg_t));
 138     memset(&curPrd.entry, 0, sizeof(PrdEntry_t));
 139
 140     dmaInterfaceBytes = 0;
 141     curPrdAddr = 0;
 142     curSector = 0;
 143     cmdBytes = 0;
 144     cmdBytesLeft = 0;
 145     drqBytesLeft = 0;
 146     dmaRead = false;
 147     intrPending = false;
 148
 149     // set the device state to idle
 150     dmaState = Dma_Idle;
 151
 152     if (id == DEV0) {
 153         devState = Device_Idle_S;
 154         devID = DEV0;
 155     } else if (id == DEV1) {
 156         devState = Device_Idle_NS;
 157         devID = DEV1;
 158     } else {
 159         panic("Invalid device ID: %#x\n", id);
 160     }
 161
 162     // set the device ready bit
 163     status = STATUS_DRDY_BIT;
 164 }
 165
 166 ////
 167 // Utility functions
 168 ////
 169
 170 Addr
 171 IdeDisk::pciToDma(Addr pciAddr)
 172 {
 173     if (ctrl)
 174         return ctrl->tsunami->pchip->translatePciToDma(pciAddr);
 175     else
 176         panic("Access to unset controller!\n");
 177 }
 178
 179 uint32_t
 180 IdeDisk::bytesInDmaPage(Addr curAddr, uint32_t bytesLeft)
 181 {
 182     uint32_t bytesInPage = 0;
 183
 184     // First calculate how many bytes could be in the page
 185     if (bytesLeft > ALPHA_PGBYTES)
 186         bytesInPage = ALPHA_PGBYTES;
 187     else
 188         bytesInPage = bytesLeft;
 189
 190     // Next, see if we have crossed a page boundary, and adjust
 191     Addr upperBound = curAddr + bytesInPage;
 192     Addr pageBound = alpha_trunc_page(curAddr) + ALPHA_PGBYTES;
 193
 194     assert(upperBound >= curAddr && "DMA read wraps around address space!\n");
 195
 196     if (upperBound >= pageBound)
 197         bytesInPage = pageBound - curAddr;
 198
 199     return bytesInPage;
 200 }
 201
 202 ////
 203 // Device registers read/write
 204 ////
 205
 206 void
 207 IdeDisk::read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data)
 208 {
 209     DevAction_t action = ACT_NONE;
 210
 211     if (cmdBlk) {
 212         if (offset < 0 || offset > sizeof(CommandReg_t))
 213             panic("Invalid disk command register offset: %#x\n", offset);
 214
 215         if (!byte && offset != DATA_OFFSET)
 216             panic("Invalid 16-bit read, only allowed on data reg\n");
 217
 218         if (!byte)
 219             *(uint16_t *)data = *(uint16_t *)&cmdReg.data0;
 220         else
 221             *data = ((uint8_t *)&cmdReg)[offset];
 222
 223         // determine if an action needs to be taken on the state machine
 224         if (offset == STATUS_OFFSET) {
 225             action = ACT_STAT_READ;
 226             *data = status; // status is in a shadow, explicity copy
 227         } else if (offset == DATA_OFFSET) {
 228             if (byte)
 229                 action = ACT_DATA_READ_BYTE;
 230             else
 231                 action = ACT_DATA_READ_SHORT;
 232         }
 233
 234     } else {
 235         if (offset != ALTSTAT_OFFSET)
 236             panic("Invalid disk control register offset: %#x\n", offset);
 237
 238         if (!byte)
 239             panic("Invalid 16-bit read from control block\n");
 240
 241         *data = status;
 242     }
 243
 244     if (action != ACT_NONE)
 245         updateState(action);
 246 }
 247
 248 void
 249 IdeDisk::write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data)
 250 {
 251     DevAction_t action = ACT_NONE;
 252
 253     if (cmdBlk) {
 254         if (offset < 0 || offset > sizeof(CommandReg_t))
 255             panic("Invalid disk command register offset: %#x\n", offset);
 256
 257         if (!byte && offset != DATA_OFFSET)
 258             panic("Invalid 16-bit write, only allowed on data reg\n");
 259
 260         if (!byte)
 261             *((uint16_t *)&cmdReg.data0) = *(uint16_t *)data;
 262         else
 263             ((uint8_t *)&cmdReg)[offset] = *data;
 264
 265         // determine if an action needs to be taken on the state machine
 266         if (offset == COMMAND_OFFSET) {
 267             action = ACT_CMD_WRITE;
 268         } else if (offset == DATA_OFFSET) {
 269             if (byte)
 270                 action = ACT_DATA_WRITE_BYTE;
 271             else
 272                 action = ACT_DATA_WRITE_SHORT;
 273         } else if (offset == SELECT_OFFSET) {
 274             action = ACT_SELECT_WRITE;
 275         }
 276
 277     } else {
 278         if (offset != CONTROL_OFFSET)
 279             panic("Invalid disk control register offset: %#x\n", offset);
 280
 281         if (!byte)
 282             panic("Invalid 16-bit write to control block\n");
 283
 284         if (*data & CONTROL_RST_BIT) {
 285             // force the device into the reset state
 286             devState = Device_Srst;
 287             action = ACT_SRST_SET;
 288         } else if (devState == Device_Srst && !(*data & CONTROL_RST_BIT)) {
 289             action = ACT_SRST_CLEAR;
 290         }
 291
 292         nIENBit = (*data & CONTROL_IEN_BIT) ? true : false;
 293     }
 294
 295     if (action != ACT_NONE)
 296         updateState(action);
 297 }
 298
 299 ////
 300 // Perform DMA transactions
 301 ////
 302
 303 void
 304 IdeDisk::doDmaTransfer()
 305 {
 306     if (dmaState != Dma_Transfer || devState != Transfer_Data_Dma)
 307         panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
 308               dmaState, devState);
 309
 310     // first read the current PRD
 311     if (dmaInterface) {
 312         if (dmaInterface->busy()) {
 313             // reschedule after waiting period
 314             dmaTransferEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
 315             return;
 316         }
 317
 318         dmaInterface->doDMA(Read, curPrdAddr, sizeof(PrdEntry_t), curTick,
 319                             &dmaPrdReadEvent);
 320     } else {
 321         dmaPrdReadDone();
 322     }
 323 }
 324
 325 void
 326 IdeDisk::dmaPrdReadDone()
 327 {
 328     // actually copy the PRD from physical memory
 329     memcpy((void *)&curPrd.entry,
 330            physmem->dma_addr(curPrdAddr, sizeof(PrdEntry_t)),
 331            sizeof(PrdEntry_t));
 332
 333     DPRINTF(IdeDisk, "PRD: baseAddr:%#x (%#x) byteCount:%d (%d) eot:%#x sector:%d\n",
 334             curPrd.getBaseAddr(), pciToDma(curPrd.getBaseAddr()),
 335             curPrd.getByteCount(), (cmdBytesLeft/SectorSize),
 336             curPrd.getEOT(), curSector);
 337
 338     // make sure the new curPrdAddr is properly translated from PCI to system
 339     curPrdAddr = pciToDma(curPrdAddr + sizeof(PrdEntry_t));
 340
 341     if (dmaRead)
 342         doDmaRead();
 343     else
 344         doDmaWrite();
 345 }
 346
 347 void
 348 IdeDisk::doDmaRead()
 349 {
 350     Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
 351
 352     if (dmaInterface) {
 353         if (dmaInterface->busy()) {
 354             // reschedule after waiting period
 355             dmaReadWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
 356             return;
 357         }
 358
 359         Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
 360
 361         uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
 362                                               (uint32_t)curPrd.getByteCount());
 363
 364         dmaInterfaceBytes = bytesInPage;
 365
 366         dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
 367                             curTick + totalDiskDelay, &dmaReadEvent);
 368     } else {
 369         // schedule dmaReadEvent with sectorDelay (dmaReadDone)
 370         dmaReadEvent.schedule(curTick + totalDiskDelay);
 371     }
 372 }
 373
 374 void
 375 IdeDisk::dmaReadDone()
 376 {
 377
 378     Addr curAddr = 0, dmaAddr = 0;
 379     uint32_t bytesWritten = 0, bytesInPage = 0, bytesLeft = 0;
 380
 381     // continue to use the DMA interface until all pages are read
 382     if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
 383         // see if the interface is busy
 384         if (dmaInterface->busy()) {
 385             // reschedule after waiting period
 386             dmaReadEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
 387             return;
 388         }
 389
 390         uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
 391         curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
 392         dmaAddr = pciToDma(curAddr);
 393
 394         bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
 395         dmaInterfaceBytes += bytesInPage;
 396
 397         dmaInterface->doDMA(Read, dmaAddr, bytesInPage,
 398                             curTick, &dmaReadEvent);
 399
 400         return;
 401     }
 402
 403     // set initial address
 404     curAddr = curPrd.getBaseAddr();
 405
 406     // clear out the data buffer
 407     memset(dataBuffer, 0, MAX_DMA_SIZE);
 408
 409     // read the data from memory via DMA into a data buffer
 410     while (bytesWritten < curPrd.getByteCount()) {
 411         if (cmdBytesLeft <= 0)
 412             panic("DMA data is larger than # of sectors specified\n");
 413
 414         dmaAddr = pciToDma(curAddr);
 415
 416         // calculate how many bytes are in the current page
 417         bytesLeft = curPrd.getByteCount() - bytesWritten;
 418         bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
 419
 420         // copy the data from memory into the data buffer
 421         memcpy((void *)(dataBuffer + bytesWritten),
 422                physmem->dma_addr(dmaAddr, bytesInPage),
 423                bytesInPage);
 424
 425         curAddr += bytesInPage;
 426         bytesWritten += bytesInPage;
 427         cmdBytesLeft -= bytesInPage;
 428     }
 429
 430     // write the data to the disk image
 431     for (bytesWritten = 0;
 432          bytesWritten < curPrd.getByteCount();
 433          bytesWritten += SectorSize) {
 434
 435         writeDisk(curSector++, (uint8_t *)(dataBuffer + bytesWritten));
 436     }
 437
 438     // check for the EOT
 439     if (curPrd.getEOT()) {
 440         assert(cmdBytesLeft == 0);
 441         dmaState = Dma_Idle;
 442         updateState(ACT_DMA_DONE);
 443     } else {
 444         doDmaTransfer();
 445     }
 446 }
 447
 448 void
 449 IdeDisk::doDmaWrite()
 450 {
 451     Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
 452
 453     if (dmaInterface) {
 454         if (dmaInterface->busy()) {
 455             // reschedule after waiting period
 456             dmaWriteWaitEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
 457             return;
 458         }
 459
 460         Addr dmaAddr = pciToDma(curPrd.getBaseAddr());
 461
 462         uint32_t bytesInPage = bytesInDmaPage(curPrd.getBaseAddr(),
 463                                               (uint32_t)curPrd.getByteCount());
 464
 465         dmaInterfaceBytes = bytesInPage;
 466
 467         dmaInterface->doDMA(WriteInvalidate, dmaAddr,
 468                             bytesInPage, curTick + totalDiskDelay,
 469                             &dmaWriteEvent);
 470     } else {
 471         // schedule event with disk delay (dmaWriteDone)
 472         dmaWriteEvent.schedule(curTick + totalDiskDelay);
 473     }
 474 }
 475
 476 void
 477 IdeDisk::dmaWriteDone()
 478 {
 479     Addr curAddr = 0, pageAddr = 0, dmaAddr = 0;
 480     uint32_t bytesRead = 0, bytesInPage = 0;
 481
 482     // continue to use the DMA interface until all pages are read
 483     if (dmaInterface && (dmaInterfaceBytes < curPrd.getByteCount())) {
 484         // see if the interface is busy
 485         if (dmaInterface->busy()) {
 486             // reschedule after waiting period
 487             dmaWriteEvent.schedule(curTick + DMA_BACKOFF_PERIOD);
 488             return;
 489         }
 490
 491         uint32_t bytesLeft = curPrd.getByteCount() - dmaInterfaceBytes;
 492         curAddr = curPrd.getBaseAddr() + dmaInterfaceBytes;
 493         dmaAddr = pciToDma(curAddr);
 494
 495         bytesInPage = bytesInDmaPage(curAddr, bytesLeft);
 496         dmaInterfaceBytes += bytesInPage;
 497
 498         dmaInterface->doDMA(WriteInvalidate, dmaAddr,
 499                             bytesInPage, curTick,
 500                             &dmaWriteEvent);
 501
 502         return;
 503     }
 504
 505     // setup the initial page and DMA address
 506     curAddr = curPrd.getBaseAddr();
 507     pageAddr = alpha_trunc_page(curAddr);
 508     dmaAddr = pciToDma(curAddr);
 509
 510     // clear out the data buffer
 511     memset(dataBuffer, 0, MAX_DMA_SIZE);
 512
 513     while (bytesRead < curPrd.getByteCount()) {
 514         // see if we have crossed into a new page
 515         if (pageAddr != alpha_trunc_page(curAddr)) {
 516             // write the data to memory
 517             memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
 518                    (void *)(dataBuffer + (bytesRead - bytesInPage)),
 519                    bytesInPage);
 520
 521             // update the DMA address and page address
 522             pageAddr = alpha_trunc_page(curAddr);
 523             dmaAddr = pciToDma(curAddr);
 524
 525             bytesInPage = 0;
 526         }
 527
 528         if (cmdBytesLeft <= 0)
 529             panic("DMA requested data is larger than # sectors specified\n");
 530
 531         readDisk(curSector++, (uint8_t *)(dataBuffer + bytesRead));
 532
 533         curAddr += SectorSize;
 534         bytesRead += SectorSize;
 535         bytesInPage += SectorSize;
 536         cmdBytesLeft -= SectorSize;
 537     }
 538
 539     // write the last page worth read to memory
 540     if (bytesInPage != 0) {
 541         memcpy(physmem->dma_addr(dmaAddr, bytesInPage),
 542                (void *)(dataBuffer + (bytesRead - bytesInPage)),
 543                bytesInPage);
 544     }
 545
 546     // check for the EOT
 547     if (curPrd.getEOT()) {
 548         assert(cmdBytesLeft == 0);
 549         dmaState = Dma_Idle;
 550         updateState(ACT_DMA_DONE);
 551     } else {
 552         doDmaTransfer();
 553     }
 554 }
 555
 556 ////
 557 // Disk utility routines
 558 ///
 559
 560 void
 561 IdeDisk::readDisk(uint32_t sector, uint8_t *data)
 562 {
 563     uint32_t bytesRead = image->read(data, sector);
 564
 565     if (bytesRead != SectorSize)
 566         panic("Can't read from %s. Only %d of %d read. errno=%d\n",
 567               name(), bytesRead, SectorSize, errno);
 568 }
 569
 570 void
 571 IdeDisk::writeDisk(uint32_t sector, uint8_t *data)
 572 {
 573     uint32_t bytesWritten = image->write(data, sector);
 574
 575     if (bytesWritten != SectorSize)
 576         panic("Can't write to %s. Only %d of %d written. errno=%d\n",
 577               name(), bytesWritten, SectorSize, errno);
 578 }
 579
 580 ////
 581 // Setup and handle commands
 582 ////
 583
 584 void
 585 IdeDisk::startDma(const uint32_t &prdTableBase)
 586 {
 587     if (dmaState != Dma_Start)
 588         panic("Inconsistent DMA state, should be in Dma_Start!\n");
 589
 590     if (devState != Transfer_Data_Dma)
 591         panic("Inconsistent device state for DMA start!\n");
 592
 593     // PRD base address is given by bits 31:2
 594     curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
 595
 596     dmaState = Dma_Transfer;
 597
 598     // schedule dma transfer (doDmaTransfer)
 599     dmaTransferEvent.schedule(curTick + 1);
 600 }
 601
 602 void
 603 IdeDisk::abortDma()
 604 {
 605     if (dmaState == Dma_Idle)
 606         panic("Inconsistent DMA state, should be in Dma_Start or Dma_Transfer!\n");
 607
 608     if (devState != Transfer_Data_Dma && devState != Prepare_Data_Dma)
 609         panic("Inconsistent device state, should be in Transfer or Prepare!\n");
 610
 611     updateState(ACT_CMD_ERROR);
 612 }
 613
 614 void
 615 IdeDisk::startCommand()
 616 {
 617     DevAction_t action = ACT_NONE;
 618     uint32_t size = 0;
 619     dmaRead = false;
 620
 621     // Decode commands
 622     switch (cmdReg.command) {
 623         // Supported non-data commands
 624       case WIN_READ_NATIVE_MAX:
 625         size = image->size() - 1;
 626         cmdReg.sec_num = (size & 0xff);
 627         cmdReg.cyl_low = ((size & 0xff00) >> 8);
 628         cmdReg.cyl_high = ((size & 0xff0000) >> 16);
 629         cmdReg.head = ((size & 0xf000000) >> 24);
 630
 631         devState = Command_Execution;
 632         action = ACT_CMD_COMPLETE;
 633         break;
 634
 635       case WIN_RECAL:
 636       case WIN_SPECIFY:
 637       case WIN_STANDBYNOW1:
 638       case WIN_FLUSH_CACHE:
 639       case WIN_VERIFY:
 640       case WIN_SEEK:
 641       case WIN_SETFEATURES:
 642       case WIN_SETMULT:
 643         devState = Command_Execution;
 644         action = ACT_CMD_COMPLETE;
 645         break;
 646
 647         // Supported PIO data-in commands
 648       case WIN_IDENTIFY:
 649         cmdBytes = cmdBytesLeft = sizeof(struct hd_driveid);
 650         devState = Prepare_Data_In;
 651         action = ACT_DATA_READY;
 652         break;
 653
 654       case WIN_MULTREAD:
 655       case WIN_READ:
 656         if (!(cmdReg.drive & DRIVE_LBA_BIT))
 657             panic("Attempt to perform CHS access, only supports LBA\n");
 658
 659         if (cmdReg.sec_count == 0)
 660             cmdBytes = cmdBytesLeft = (256 * SectorSize);
 661         else
 662             cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
 663
 664         curSector = getLBABase();
 665
 666         /** @todo make this a scheduled event to simulate disk delay */
 667         devState = Prepare_Data_In;
 668         action = ACT_DATA_READY;
 669         break;
 670
 671         // Supported PIO data-out commands
 672       case WIN_MULTWRITE:
 673       case WIN_WRITE:
 674         if (!(cmdReg.drive & DRIVE_LBA_BIT))
 675             panic("Attempt to perform CHS access, only supports LBA\n");
 676
 677         if (cmdReg.sec_count == 0)
 678             cmdBytes = cmdBytesLeft = (256 * SectorSize);
 679         else
 680             cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
 681
 682         curSector = getLBABase();
 683
 684         devState = Prepare_Data_Out;
 685         action = ACT_DATA_READY;
 686         break;
 687
 688         // Supported DMA commands
 689       case WIN_WRITEDMA:
 690         dmaRead = true;  // a write to the disk is a DMA read from memory
 691       case WIN_READDMA:
 692         if (!(cmdReg.drive & DRIVE_LBA_BIT))
 693             panic("Attempt to perform CHS access, only supports LBA\n");
 694
 695         if (cmdReg.sec_count == 0)
 696             cmdBytes = cmdBytesLeft = (256 * SectorSize);
 697         else
 698             cmdBytes = cmdBytesLeft = (cmdReg.sec_count * SectorSize);
 699
 700         curSector = getLBABase();
 701
 702         devState = Prepare_Data_Dma;
 703         action = ACT_DMA_READY;
 704         break;
 705
 706       default:
 707         panic("Unsupported ATA command: %#x\n", cmdReg.command);
 708     }
 709
 710     if (action != ACT_NONE) {
 711         // set the BSY bit
 712         status |= STATUS_BSY_BIT;
 713         // clear the DRQ bit
 714         status &= ~STATUS_DRQ_BIT;
 715         // clear the DF bit
 716         status &= ~STATUS_DF_BIT;
 717
 718         updateState(action);
 719     }
 720 }
 721
 722 ////
 723 // Handle setting and clearing interrupts
 724 ////
 725
 726 void
 727 IdeDisk::intrPost()
 728 {
 729     if (intrPending)
 730         panic("Attempt to post an interrupt with one pending\n");
 731
 732     intrPending = true;
 733
 734     // talk to controller to set interrupt
 735     if (ctrl)
 736         ctrl->intrPost();
 737 }
 738
 739 void
 740 IdeDisk::intrClear()
 741 {
 742     if (!intrPending)
 743         panic("Attempt to clear a non-pending interrupt\n");
 744
 745     intrPending = false;
 746
 747     // talk to controller to clear interrupt
 748     if (ctrl)
 749         ctrl->intrClear();
 750 }
 751
 752 ////
 753 // Manage the device internal state machine
 754 ////
 755
 756 void
 757 IdeDisk::updateState(DevAction_t action)
 758 {
 759     switch (devState) {
 760       case Device_Srst:
 761         if (action == ACT_SRST_SET) {
 762             // set the BSY bit
 763             status |= STATUS_BSY_BIT;
 764         } else if (action == ACT_SRST_CLEAR) {
 765             // clear the BSY bit
 766             status &= ~STATUS_BSY_BIT;
 767
 768             // reset the device state
 769             reset(devID);
 770         }
 771         break;
 772
 773       case Device_Idle_S:
 774         if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
 775             devState = Device_Idle_NS;
 776         } else if (action == ACT_CMD_WRITE) {
 777             startCommand();
 778         }
 779
 780         break;
 781
 782       case Device_Idle_SI:
 783         if (action == ACT_SELECT_WRITE && !isDEVSelect()) {
 784             devState = Device_Idle_NS;
 785             intrClear();
 786         } else if (action == ACT_STAT_READ || isIENSet()) {
 787             devState = Device_Idle_S;
 788             intrClear();
 789         } else if (action == ACT_CMD_WRITE) {
 790             intrClear();
 791             startCommand();
 792         }
 793
 794         break;
 795
 796       case Device_Idle_NS:
 797         if (action == ACT_SELECT_WRITE && isDEVSelect()) {
 798             if (!isIENSet() && intrPending) {
 799                 devState = Device_Idle_SI;
 800                 intrPost();
 801             }
 802             if (isIENSet() || !intrPending) {
 803                 devState = Device_Idle_S;
 804             }
 805         }
 806         break;
 807
 808       case Command_Execution:
 809         if (action == ACT_CMD_COMPLETE) {
 810             // clear the BSY bit
 811             setComplete();
 812
 813             if (!isIENSet()) {
 814                 devState = Device_Idle_SI;
 815                 intrPost();
 816             } else {
 817                 devState = Device_Idle_S;
 818             }
 819         }
 820         break;
 821
 822       case Prepare_Data_In:
 823         if (action == ACT_CMD_ERROR) {
 824             // clear the BSY bit
 825             setComplete();
 826
 827             if (!isIENSet()) {
 828                 devState = Device_Idle_SI;
 829                 intrPost();
 830             } else {
 831                 devState = Device_Idle_S;
 832             }
 833         } else if (action == ACT_DATA_READY) {
 834             // clear the BSY bit
 835             status &= ~STATUS_BSY_BIT;
 836             // set the DRQ bit
 837             status |= STATUS_DRQ_BIT;
 838
 839             // copy the data into the data buffer
 840             if (cmdReg.command == WIN_IDENTIFY) {
 841                 // Reset the drqBytes for this block
 842                 drqBytesLeft = sizeof(struct hd_driveid);
 843
 844                 memcpy((void *)dataBuffer, (void *)&driveID,
 845                        sizeof(struct hd_driveid));
 846             } else {
 847                 // Reset the drqBytes for this block
 848                 drqBytesLeft = SectorSize;
 849
 850                 readDisk(curSector++, dataBuffer);
 851             }
 852
 853             // put the first two bytes into the data register
 854             memcpy((void *)&cmdReg.data0, (void *)dataBuffer,
 855                    sizeof(uint16_t));
 856
 857             if (!isIENSet()) {
 858                 devState = Data_Ready_INTRQ_In;
 859                 intrPost();
 860             } else {
 861                 devState = Transfer_Data_In;
 862             }
 863         }
 864         break;
 865
 866       case Data_Ready_INTRQ_In:
 867         if (action == ACT_STAT_READ) {
 868             devState = Transfer_Data_In;
 869             intrClear();
 870         }
 871         break;
 872
 873       case Transfer_Data_In:
 874         if (action == ACT_DATA_READ_BYTE || action == ACT_DATA_READ_SHORT) {
 875             if (action == ACT_DATA_READ_BYTE) {
 876                 panic("DEBUG: READING DATA ONE BYTE AT A TIME!\n");
 877             } else {
 878                 drqBytesLeft -= 2;
 879                 cmdBytesLeft -= 2;
 880
 881                 // copy next short into data registers
 882                 if (drqBytesLeft)
 883                     memcpy((void *)&cmdReg.data0,
 884                            (void *)&dataBuffer[SectorSize - drqBytesLeft],
 885                            sizeof(uint16_t));
 886             }
 887
 888             if (drqBytesLeft == 0) {
 889                 if (cmdBytesLeft == 0) {
 890                     // Clear the BSY bit
 891                     setComplete();
 892                     devState = Device_Idle_S;
 893                 } else {
 894                     devState = Prepare_Data_In;
 895                     // set the BSY_BIT
 896                     status |= STATUS_BSY_BIT;
 897                     // clear the DRQ_BIT
 898                     status &= ~STATUS_DRQ_BIT;
 899
 900                     /** @todo change this to a scheduled event to simulate
 901                         disk delay */
 902                     updateState(ACT_DATA_READY);
 903                 }
 904             }
 905         }
 906         break;
 907
 908       case Prepare_Data_Out:
 909         if (action == ACT_CMD_ERROR || cmdBytesLeft == 0) {
 910             // clear the BSY bit
 911             setComplete();
 912
 913             if (!isIENSet()) {
 914                 devState = Device_Idle_SI;
 915                 intrPost();
 916             } else {
 917                 devState = Device_Idle_S;
 918             }
 919         } else if (action == ACT_DATA_READY && cmdBytesLeft != 0) {
 920             // clear the BSY bit
 921             status &= ~STATUS_BSY_BIT;
 922             // set the DRQ bit
 923             status |= STATUS_DRQ_BIT;
 924
 925             // clear the data buffer to get it ready for writes
 926             memset(dataBuffer, 0, MAX_DMA_SIZE);
 927
 928             // reset the drqBytes for this block
 929             drqBytesLeft = SectorSize;
 930
 931             if (cmdBytesLeft == cmdBytes || isIENSet()) {
 932                 devState = Transfer_Data_Out;
 933             } else {
 934                 devState = Data_Ready_INTRQ_Out;
 935                 intrPost();
 936             }
 937         }
 938         break;
 939
 940       case Data_Ready_INTRQ_Out:
 941         if (action == ACT_STAT_READ) {
 942             devState = Transfer_Data_Out;
 943             intrClear();
 944         }
 945         break;
 946
 947       case Transfer_Data_Out:
 948         if (action == ACT_DATA_WRITE_BYTE ||
 949             action == ACT_DATA_WRITE_SHORT) {
 950
 951             if (action == ACT_DATA_READ_BYTE) {
 952                 panic("DEBUG: WRITING DATA ONE BYTE AT A TIME!\n");
 953             } else {
 954                 // copy the latest short into the data buffer
 955                 memcpy((void *)&dataBuffer[SectorSize - drqBytesLeft],
 956                        (void *)&cmdReg.data0,
 957                        sizeof(uint16_t));
 958
 959                 drqBytesLeft -= 2;
 960                 cmdBytesLeft -= 2;
 961             }
 962
 963             if (drqBytesLeft == 0) {
 964                 // copy the block to the disk
 965                 writeDisk(curSector++, dataBuffer);
 966
 967                 // set the BSY bit
 968                 status |= STATUS_BSY_BIT;
 969                 // set the seek bit
 970                 status |= STATUS_SEEK_BIT;
 971                 // clear the DRQ bit
 972                 status &= ~STATUS_DRQ_BIT;
 973
 974                 devState = Prepare_Data_Out;
 975
 976                 /** @todo change this to a scheduled event to simulate
 977                     disk delay */
 978                 updateState(ACT_DATA_READY);
 979             }
 980         }
 981         break;
 982
 983       case Prepare_Data_Dma:
 984         if (action == ACT_CMD_ERROR) {
 985             // clear the BSY bit
 986             setComplete();
 987
 988             if (!isIENSet()) {
 989                 devState = Device_Idle_SI;
 990                 intrPost();
 991             } else {
 992                 devState = Device_Idle_S;
 993             }
 994         } else if (action == ACT_DMA_READY) {
 995             // clear the BSY bit
 996             status &= ~STATUS_BSY_BIT;
 997             // set the DRQ bit
 998             status |= STATUS_DRQ_BIT;
 999
1000             devState = Transfer_Data_Dma;
1001
1002             if (dmaState != Dma_Idle)
1003                 panic("Inconsistent DMA state, should be Dma_Idle\n");
1004
1005             dmaState = Dma_Start;
1006             // wait for the write to the DMA start bit
1007         }
1008         break;
1009
1010       case Transfer_Data_Dma:
1011         if (action == ACT_CMD_ERROR || action == ACT_DMA_DONE) {
1012             // clear the BSY bit
1013             setComplete();
1014             // set the seek bit
1015             status |= STATUS_SEEK_BIT;
1016             // clear the controller state for DMA transfer
1017             ctrl->setDmaComplete(this);
1018
1019             if (!isIENSet()) {
1020                 devState = Device_Idle_SI;
1021                 intrPost();
1022             } else {
1023                 devState = Device_Idle_S;
1024             }
1025         }
1026         break;
1027
1028       default:
1029         panic("Unknown IDE device state: %#x\n", devState);
1030     }
1031 }
1032
1033 void
1034 IdeDisk::serialize(ostream &os)
1035 {
1036     // Check all outstanding events to see if they are scheduled
1037     // these are all mutually exclusive
1038     Tick reschedule = 0;
1039     Events_t event = None;
1040
1041     int eventCount = 0;
1042
1043     if (dmaTransferEvent.scheduled()) {
1044         reschedule = dmaTransferEvent.when();
1045         event = Transfer;
1046         eventCount++;
1047     }
1048     if (dmaReadWaitEvent.scheduled()) {
1049         reschedule = dmaReadWaitEvent.when();
1050         event = ReadWait;
1051         eventCount++;
1052     }
1053     if (dmaWriteWaitEvent.scheduled()) {
1054         reschedule = dmaWriteWaitEvent.when();
1055         event = WriteWait;
1056         eventCount++;
1057     }
1058     if (dmaPrdReadEvent.scheduled()) {
1059         reschedule = dmaPrdReadEvent.when();
1060         event = PrdRead;
1061         eventCount++;
1062     }
1063     if (dmaReadEvent.scheduled()) {
1064         reschedule = dmaReadEvent.when();
1065         event = DmaRead;
1066         eventCount++;
1067     }
1068     if (dmaWriteEvent.scheduled()) {
1069         reschedule = dmaWriteEvent.when();
1070         event = DmaWrite;
1071         eventCount++;
1072     }
1073
1074     assert(eventCount <= 1);
1075
1076     SERIALIZE_SCALAR(reschedule);
1077     SERIALIZE_ENUM(event);
1078
1079     // Serialize device registers
1080     SERIALIZE_SCALAR(cmdReg.data0);
1081     SERIALIZE_SCALAR(cmdReg.data1);
1082     SERIALIZE_SCALAR(cmdReg.sec_count);
1083     SERIALIZE_SCALAR(cmdReg.sec_num);
1084     SERIALIZE_SCALAR(cmdReg.cyl_low);
1085     SERIALIZE_SCALAR(cmdReg.cyl_high);
1086     SERIALIZE_SCALAR(cmdReg.drive);
1087     SERIALIZE_SCALAR(cmdReg.command);
1088     SERIALIZE_SCALAR(status);
1089     SERIALIZE_SCALAR(nIENBit);
1090     SERIALIZE_SCALAR(devID);
1091
1092     // Serialize the PRD related information
1093     SERIALIZE_SCALAR(curPrd.entry.baseAddr);
1094     SERIALIZE_SCALAR(curPrd.entry.byteCount);
1095     SERIALIZE_SCALAR(curPrd.entry.endOfTable);
1096     SERIALIZE_SCALAR(curPrdAddr);
1097
1098     // Serialize current transfer related information
1099     SERIALIZE_SCALAR(cmdBytesLeft);
1100     SERIALIZE_SCALAR(cmdBytes);
1101     SERIALIZE_SCALAR(drqBytesLeft);
1102     SERIALIZE_SCALAR(curSector);
1103     SERIALIZE_SCALAR(dmaRead);
1104     SERIALIZE_SCALAR(dmaInterfaceBytes);
1105     SERIALIZE_SCALAR(intrPending);
1106     SERIALIZE_ENUM(devState);
1107     SERIALIZE_ENUM(dmaState);
1108     SERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
1109 }
1110
1111 void
1112 IdeDisk::unserialize(Checkpoint *cp, const string &section)
1113 {
1114     // Reschedule events that were outstanding
1115     // these are all mutually exclusive
1116     Tick reschedule = 0;
1117     Events_t event = None;
1118
1119     UNSERIALIZE_SCALAR(reschedule);
1120     UNSERIALIZE_ENUM(event);
1121
1122     switch (event) {
1123       case None : break;
1124       case Transfer : dmaTransferEvent.schedule(reschedule); break;
1125       case ReadWait : dmaReadWaitEvent.schedule(reschedule); break;
1126       case WriteWait : dmaWriteWaitEvent.schedule(reschedule); break;
1127       case PrdRead : dmaPrdReadEvent.schedule(reschedule); break;
1128       case DmaRead : dmaReadEvent.schedule(reschedule); break;
1129       case DmaWrite : dmaWriteEvent.schedule(reschedule); break;
1130     }
1131
1132     // Unserialize device registers
1133     UNSERIALIZE_SCALAR(cmdReg.data0);
1134     UNSERIALIZE_SCALAR(cmdReg.data1);
1135     UNSERIALIZE_SCALAR(cmdReg.sec_count);
1136     UNSERIALIZE_SCALAR(cmdReg.sec_num);
1137     UNSERIALIZE_SCALAR(cmdReg.cyl_low);
1138     UNSERIALIZE_SCALAR(cmdReg.cyl_high);
1139     UNSERIALIZE_SCALAR(cmdReg.drive);
1140     UNSERIALIZE_SCALAR(cmdReg.command);
1141     UNSERIALIZE_SCALAR(status);
1142     UNSERIALIZE_SCALAR(nIENBit);
1143     UNSERIALIZE_SCALAR(devID);
1144
1145     // Unserialize the PRD related information
1146     UNSERIALIZE_SCALAR(curPrd.entry.baseAddr);
1147     UNSERIALIZE_SCALAR(curPrd.entry.byteCount);
1148     UNSERIALIZE_SCALAR(curPrd.entry.endOfTable);
1149     UNSERIALIZE_SCALAR(curPrdAddr);
1150
1151     // Unserialize current transfer related information
1152     UNSERIALIZE_SCALAR(cmdBytes);
1153     UNSERIALIZE_SCALAR(cmdBytesLeft);
1154     UNSERIALIZE_SCALAR(drqBytesLeft);
1155     UNSERIALIZE_SCALAR(curSector);
1156     UNSERIALIZE_SCALAR(dmaRead);
1157     UNSERIALIZE_SCALAR(dmaInterfaceBytes);
1158     UNSERIALIZE_SCALAR(intrPending);
1159     UNSERIALIZE_ENUM(devState);
1160     UNSERIALIZE_ENUM(dmaState);
1161     UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
1162 }
1163
1164 #ifndef DOXYGEN_SHOULD_SKIP_THIS
1165
1166 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
1167
1168     SimObjectParam<DiskImage *> image;
1169     SimObjectParam<PhysicalMemory *> physmem;
1170     Param<int> driveID;
1171     Param<int> disk_delay;
1172
1173 END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
1174
1175 BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
1176
1177     INIT_PARAM(image, "Disk image"),
1178     INIT_PARAM(physmem, "Physical memory"),
1179     INIT_PARAM(driveID, "Drive ID (0=master 1=slave)"),
1180     INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in microseconds", 1)
1181
1182 END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
1183
1184
1185 CREATE_SIM_OBJECT(IdeDisk)
1186 {
1187     return new IdeDisk(getInstanceName(), image, physmem, driveID,
1188                        disk_delay);
1189 }
1190
1191 REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
1192
1193 #endif //DOXYGEN_SHOULD_SKIP_THIS