2 * Copyright (c) 2003 The Regents of The University of Michigan
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30 * Device model for an IDE disk
33 #ifndef __IDE_DISK_HH__
34 #define __IDE_DISK_HH__
37 #include "dev/disk_image.hh"
38 #include "dev/io_device.hh"
39 #include "sim/eventq.hh"
41 #define DMA_BACKOFF_PERIOD 200
43 #define MAX_DMA_SIZE (131072) // 256 * SectorSize (512)
44 #define MAX_MULTSECT (128)
46 #define PRD_BASE_MASK 0xfffffffe
47 #define PRD_COUNT_MASK 0xfffe
48 #define PRD_EOT_MASK 0x8000
50 typedef struct PrdEntry {
60 uint32_t getBaseAddr()
62 return (entry.baseAddr & PRD_BASE_MASK);
65 uint16_t getByteCount()
67 return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
68 (entry.byteCount & PRD_COUNT_MASK));
73 return (entry.endOfTable & PRD_EOT_MASK);
77 #define DATA_OFFSET (0)
78 #define ERROR_OFFSET (1)
79 #define FEATURES_OFFSET (1)
80 #define NSECTOR_OFFSET (2)
81 #define SECTOR_OFFSET (3)
82 #define LCYL_OFFSET (4)
83 #define HCYL_OFFSET (5)
84 #define SELECT_OFFSET (6)
85 #define STATUS_OFFSET (7)
86 #define COMMAND_OFFSET (7)
88 #define CONTROL_OFFSET (2)
89 #define ALTSTAT_OFFSET (2)
91 #define SELECT_DEV_BIT 0x10
92 #define CONTROL_RST_BIT 0x04
93 #define CONTROL_IEN_BIT 0x02
94 #define STATUS_BSY_BIT 0x80
95 #define STATUS_DRDY_BIT 0x40
96 #define STATUS_DRQ_BIT 0x08
97 #define DRIVE_LBA_BIT 0x40
102 typedef struct CommandReg {
123 typedef enum DevAction {
133 ACT_DATA_WRITE_SHORT,
138 typedef enum DevState {
147 // PIO data-in (data to host)
152 // PIO data-out (data from host)
154 Data_Ready_INTRQ_Out,
162 typedef enum DmaState {
168 class PhysicalMemory;
172 * IDE Disk device model
174 class IdeDisk : public SimObject
177 /** The IDE controller for this disk. */
179 /** The DMA interface to use for transfers */
180 DMAInterface<Bus> *dmaInterface;
181 /** The image that contains the data of this disk. */
183 /** Pointer to physical memory for DMA transfers */
184 PhysicalMemory *physmem;
187 /** The disk delay in milliseconds. */
191 /** Drive identification structure for this disk */
192 struct hd_driveid driveID;
193 /** Data buffer for transfers */
195 /** Number of bytes left in command data transfer */
196 uint32_t cmdBytesLeft;
197 /** Number of bytes left in DRQ block */
198 uint32_t drqBytesLeft;
199 /** Current sector in access */
201 /** Command block registers */
203 /** Shadow of the current command code */
205 /** Interrupt enable bit */
211 /** Dma transaction is a read */
213 /** PRD table base address */
216 PrdTableEntry curPrd;
217 /** Device ID (master=0/slave=1) */
219 /** Interrupt pending */
224 * Create and initialize this Disk.
225 * @param name The name of this disk.
226 * @param img The disk image of this disk.
227 * @param phys Pointer to physical memory
228 * @param id The disk ID (master=0/slave=1)
229 * @param disk_delay The disk delay in milliseconds
231 IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
232 int id, int disk_delay);
235 * Delete the data buffer.
240 * Set the controller for this device
241 * @param c The IDE controller
243 void setController(IdeController *c, DMAInterface<Bus> *dmaIntr) {
244 if (ctrl) panic("Cannot change the controller once set!\n");
246 dmaInterface = dmaIntr;
249 // Device register read/write
250 void read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data);
251 void write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data);
253 // Start/abort functions
254 void startDma(const uint32_t &prdTableBase);
260 // Interrupt management
265 void doDmaTransfer();
266 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
267 EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
270 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
271 EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
274 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
275 EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
277 void dmaPrdReadDone();
278 friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
279 EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
282 friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
283 EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
286 friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
287 EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
289 // Disk image read/write
290 void readDisk(uint32_t sector, uint8_t *data);
291 void writeDisk(uint32_t sector, uint8_t *data);
293 // State machine management
294 void updateState(DevAction_t action);
297 bool isBSYSet() { return (cmdReg.status & STATUS_BSY_BIT); }
298 bool isIENSet() { return nIENBit; }
299 bool isDEVSelect() { return ((cmdReg.drive & SELECT_DEV_BIT) == devID); }
303 // clear out the status byte
307 cmdReg.status |= STATUS_DRDY_BIT;
310 uint32_t getLBABase()
312 return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
313 (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
316 inline Addr pciToDma(Addr &pciAddr);
319 * Serialize this object to the given output stream.
320 * @param os The stream to serialize to.
322 void serialize(std::ostream &os);
325 * Reconstruct the state of this object from a checkpoint.
326 * @param cp The checkpoint to use.
327 * @param section The section name describing this object.
329 void unserialize(Checkpoint *cp, const std::string §ion);
333 #endif // __IDE_DISK_HH__