2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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30 * Device model for an IDE disk
33 #ifndef __IDE_DISK_HH__
34 #define __IDE_DISK_HH__
36 #include "dev/disk_image.hh"
37 #include "dev/ide_atareg.h"
38 #include "dev/ide_ctrl.hh"
39 #include "dev/ide_wdcreg.h"
40 #include "dev/io_device.hh"
41 #include "sim/eventq.hh"
43 #define DMA_BACKOFF_PERIOD 200
45 #define MAX_DMA_SIZE (65536) // 64K
46 #define MAX_MULTSECT (128)
48 #define PRD_BASE_MASK 0xfffffffe
49 #define PRD_COUNT_MASK 0xfffe
50 #define PRD_EOT_MASK 0x8000
52 typedef struct PrdEntry {
62 uint32_t getBaseAddr()
64 return (entry.baseAddr & PRD_BASE_MASK);
67 uint32_t getByteCount()
69 return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
70 (entry.byteCount & PRD_COUNT_MASK));
75 return (entry.endOfTable & PRD_EOT_MASK);
79 #define DATA_OFFSET (0)
80 #define ERROR_OFFSET (1)
81 #define FEATURES_OFFSET (1)
82 #define NSECTOR_OFFSET (2)
83 #define SECTOR_OFFSET (3)
84 #define LCYL_OFFSET (4)
85 #define HCYL_OFFSET (5)
86 #define SELECT_OFFSET (6)
87 #define DRIVE_OFFSET (6)
88 #define STATUS_OFFSET (7)
89 #define COMMAND_OFFSET (7)
91 #define CONTROL_OFFSET (2)
92 #define ALTSTAT_OFFSET (2)
94 #define SELECT_DEV_BIT 0x10
95 #define CONTROL_RST_BIT 0x04
96 #define CONTROL_IEN_BIT 0x02
97 #define STATUS_BSY_BIT 0x80
98 #define STATUS_DRDY_BIT 0x40
99 #define STATUS_DRQ_BIT 0x08
100 #define STATUS_SEEK_BIT 0x10
101 #define STATUS_DF_BIT 0x20
102 #define DRIVE_LBA_BIT 0x40
107 typedef struct CommandReg {
121 typedef enum Events {
131 typedef enum DevAction {
142 ACT_DATA_WRITE_SHORT,
149 typedef enum DevState {
161 // PIO data-in (data to host)
166 // PIO data-out (data from host)
168 Data_Ready_INTRQ_Out,
176 typedef enum DmaState {
182 class PhysicalMemory;
186 * IDE Disk device model
188 class IdeDisk : public SimObject
191 /** The IDE controller for this disk. */
193 /** The DMA interface to use for transfers */
194 DMAInterface<Bus> *dmaInterface;
195 /** The image that contains the data of this disk. */
197 /** Pointer to physical memory for DMA transfers */
198 PhysicalMemory *physmem;
201 /** The disk delay in microseconds. */
205 /** Drive identification structure for this disk */
206 struct ataparams driveID;
207 /** Data buffer for transfers */
209 /** Number of bytes in command data transfer */
211 /** Number of bytes left in command data transfer */
212 uint32_t cmdBytesLeft;
213 /** Number of bytes left in DRQ block */
214 uint32_t drqBytesLeft;
215 /** Current sector in access */
217 /** Command block registers */
219 /** Status register */
221 /** Interrupt enable bit */
227 /** Dma transaction is a read */
229 /** PRD table base address */
232 PrdTableEntry curPrd;
233 /** Number of bytes transfered by DMA interface for current transfer */
234 uint32_t dmaInterfaceBytes;
235 /** Device ID (master=0/slave=1) */
237 /** Interrupt pending */
242 * Create and initialize this Disk.
243 * @param name The name of this disk.
244 * @param img The disk image of this disk.
245 * @param phys Pointer to physical memory
246 * @param id The disk ID (master=0/slave=1)
247 * @param disk_delay The disk delay in milliseconds
249 IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
250 int id, Tick disk_delay);
253 * Delete the data buffer.
258 * Reset the device state
263 * Set the controller for this device
264 * @param c The IDE controller
266 void setController(IdeController *c, DMAInterface<Bus> *dmaIntr) {
267 if (ctrl) panic("Cannot change the controller once set!\n");
269 dmaInterface = dmaIntr;
272 // Device register read/write
273 void read(const Addr &offset, IdeRegType regtype, uint8_t *data);
274 void write(const Addr &offset, IdeRegType regtype, const uint8_t *data);
276 // Start/abort functions
277 void startDma(const uint32_t &prdTableBase);
283 // Interrupt management
288 void doDmaTransfer();
289 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
290 EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
293 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
294 EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
297 friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
298 EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
300 void dmaPrdReadDone();
301 friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
302 EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
305 friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
306 EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
309 friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
310 EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
312 // Disk image read/write
313 void readDisk(uint32_t sector, uint8_t *data);
314 void writeDisk(uint32_t sector, uint8_t *data);
316 // State machine management
317 void updateState(DevAction_t action);
320 bool isBSYSet() { return (status & STATUS_BSY_BIT); }
321 bool isIENSet() { return nIENBit; }
326 // clear out the status byte
329 status |= STATUS_DRDY_BIT;
331 status |= STATUS_SEEK_BIT;
334 uint32_t getLBABase()
336 return (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
337 (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
340 inline Addr pciToDma(Addr pciAddr);
342 uint32_t bytesInDmaPage(Addr curAddr, uint32_t bytesLeft);
345 * Serialize this object to the given output stream.
346 * @param os The stream to serialize to.
348 void serialize(std::ostream &os);
351 * Reconstruct the state of this object from a checkpoint.
352 * @param cp The checkpoint to use.
353 * @param section The section name describing this object.
355 void unserialize(Checkpoint *cp, const std::string §ion);
359 #endif // __IDE_DISK_HH__