dev/isa_fake.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Isa Fake Device implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "dev/isa_fake.hh"
  40 #include "mem/bus/bus.hh"
  41 #include "mem/bus/pio_interface.hh"
  42 #include "mem/bus/pio_interface_impl.hh"
  43 #include "mem/functional/memory_control.hh"
  44 #include "sim/builder.hh"
  45 #include "sim/system.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49
  50 IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
  51                          HierParams *hier, Bus *pio_bus, Addr size)
  52     : PioDevice(name, NULL), addr(a)
  53 {
  54     mmu->add_child(this, RangeSize(addr, size));
  55
  56     if (pio_bus) {
  57         pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
  58                                       &IsaFake::cacheAccess);
  59         pioInterface->addAddrRange(RangeSize(addr, size));
  60     }
  61 }
  62
  63 Fault
  64 IsaFake::read(MemReqPtr &req, uint8_t *data)
  65 {
  66     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
  67             req->vaddr, req->size);
  68
  69 #if TRACING_ON
  70     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
  71 #endif
  72
  73     switch (req->size) {
  74
  75       case sizeof(uint64_t):
  76          *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
  77          return NoFault;
  78       case sizeof(uint32_t):
  79          *(uint32_t*)data = 0xFFFFFFFF;
  80          return NoFault;
  81       case sizeof(uint16_t):
  82          *(uint16_t*)data = 0xFFFF;
  83          return NoFault;
  84       case sizeof(uint8_t):
  85          *(uint8_t*)data = 0xFF;
  86          return NoFault;
  87
  88       default:
  89         panic("invalid access size(?) for PCI configspace!\n");
  90     }
  91     DPRINTFN("Isa FakeSMC  ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
  92
  93     return NoFault;
  94 }
  95
  96 Fault
  97 IsaFake::write(MemReqPtr &req, const uint8_t *data)
  98 {
  99     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
 100             req->vaddr, req->size);
 101
 102     //:Addr daddr = (req->paddr & addr_mask) >> 6;
 103
 104     return NoFault;
 105 }
 106
 107 Tick
 108 IsaFake::cacheAccess(MemReqPtr &req)
 109 {
 110     return curTick;
 111 }
 112
 113 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
 114
 115     SimObjectParam<MemoryController *> mmu;
 116     Param<Addr> addr;
 117     SimObjectParam<Bus*> pio_bus;
 118     Param<Tick> pio_latency;
 119     SimObjectParam<HierParams *> hier;
 120     Param<Addr> size;
 121
 122 END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
 123
 124 BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
 125
 126     INIT_PARAM(mmu, "Memory Controller"),
 127     INIT_PARAM(addr, "Device Address"),
 128     INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
 129     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 130     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
 131     INIT_PARAM_DFLT(size, "Size of address range", 0x8)
 132
 133 END_INIT_SIM_OBJECT_PARAMS(IsaFake)
 134
 135 CREATE_SIM_OBJECT(IsaFake)
 136 {
 137     return new IsaFake(getInstanceName(), addr, mmu, hier, pio_bus, size);
 138 }
 139
 140 REGISTER_SIM_OBJECT("IsaFake", IsaFake)