dev/isa_fake.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Isa Fake Device implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "dev/isa_fake.hh"
  40 #include "mem/bus/bus.hh"
  41 #include "mem/bus/pio_interface.hh"
  42 #include "mem/bus/pio_interface_impl.hh"
  43 #include "mem/functional/memory_control.hh"
  44 #include "sim/builder.hh"
  45 #include "sim/system.hh"
  46
  47 using namespace std;
  48
  49 IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
  50                          HierParams *hier, Bus *bus, Addr size)
  51     : PioDevice(name, NULL), addr(a)
  52 {
  53     mmu->add_child(this, RangeSize(addr, size));
  54
  55     if (bus) {
  56         pioInterface = newPioInterface(name + ".pio", hier, bus, this,
  57                                       &IsaFake::cacheAccess);
  58         pioInterface->addAddrRange(RangeSize(addr, size));
  59     }
  60 }
  61
  62 Fault
  63 IsaFake::read(MemReqPtr &req, uint8_t *data)
  64 {
  65     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
  66             req->vaddr, req->size);
  67
  68 #if TRACING_ON
  69     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
  70 #endif
  71
  72     switch (req->size) {
  73
  74       case sizeof(uint64_t):
  75          *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
  76          return No_Fault;
  77       case sizeof(uint32_t):
  78          *(uint32_t*)data = 0xFFFFFFFF;
  79          return No_Fault;
  80       case sizeof(uint16_t):
  81          *(uint16_t*)data = 0xFFFF;
  82          return No_Fault;
  83       case sizeof(uint8_t):
  84          *(uint8_t*)data = 0xFF;
  85          return No_Fault;
  86
  87       default:
  88         panic("invalid access size(?) for PCI configspace!\n");
  89     }
  90     DPRINTFN("Isa FakeSMC  ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
  91
  92     return No_Fault;
  93 }
  94
  95 Fault
  96 IsaFake::write(MemReqPtr &req, const uint8_t *data)
  97 {
  98     DPRINTF(Tsunami, "write - va=%#x size=%d \n",
  99             req->vaddr, req->size);
 100
 101     //:Addr daddr = (req->paddr & addr_mask) >> 6;
 102
 103     return No_Fault;
 104 }
 105
 106 Tick
 107 IsaFake::cacheAccess(MemReqPtr &req)
 108 {
 109     return curTick;
 110 }
 111
 112 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
 113
 114     SimObjectParam<MemoryController *> mmu;
 115     Param<Addr> addr;
 116     SimObjectParam<Bus*> io_bus;
 117     Param<Tick> pio_latency;
 118     SimObjectParam<HierParams *> hier;
 119     Param<Addr> size;
 120
 121 END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
 122
 123 BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
 124
 125     INIT_PARAM(mmu, "Memory Controller"),
 126     INIT_PARAM(addr, "Device Address"),
 127     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 128     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
 129     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
 130     INIT_PARAM_DFLT(size, "Size of address range", 0x8)
 131
 132 END_INIT_SIM_OBJECT_PARAMS(IsaFake)
 133
 134 CREATE_SIM_OBJECT(IsaFake)
 135 {
 136     return new IsaFake(getInstanceName(), addr, mmu, hier, io_bus, size);
 137 }
 138
 139 REGISTER_SIM_OBJECT("IsaFake", IsaFake)