2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __NS_GIGE_HH__
35 #define __NS_GIGE_HH__
37 //#include "base/range.hh"
38 #include "dev/etherint.hh"
39 #include "dev/etherpkt.hh"
40 #include "sim/eventq.hh"
41 #include "dev/ns_gige_reg.h"
42 #include "base/statistics.hh"
43 #include "dev/pcidev.hh"
44 #include "dev/tsunami.hh"
45 #include "dev/io_device.hh"
46 #include "mem/bus/bus.hh"
48 /** defined by the NS83820 data sheet */
49 #define MAX_TX_FIFO_SIZE 8192
50 #define MAX_RX_FIFO_SIZE 32768
52 /** length of ethernet address in bytes */
56 * Ethernet device registers
94 /** for perfect match memory. the linux driver doesn't use any other ROM */
95 uint8_t perfectMatch[EADDR_LEN];
100 class PhysicalMemory;
107 * NS DP82830 Ethernet device model
109 class NSGigE : public PciDev
112 /** Transmit State Machine states */
124 /** Receive State Machine States */
146 /** pointer to the chipset */
151 static const Addr size = sizeof(dp_regs);
154 typedef std::deque<PacketPtr> pktbuf_t;
155 typedef pktbuf_t::iterator pktiter_t;
157 /** device register file */
168 /*** BASIC STRUCTURES FOR TX/RX ***/
173 /** various helper vars */
176 uint8_t *txPacketBufPtr;
177 uint8_t *rxPacketBufPtr;
187 /* tx State Machine */
189 /** Current Transmit Descriptor Done */
191 /** current amt of free space in txDataFifo in bytes */
192 uint32_t txFifoAvail;
193 /** halt the tx state machine after next packet */
195 /** ptr to the next byte in the current fragment */
197 /** count of bytes remaining in the current descriptor */
201 /** rx State Machine */
203 /** Current Receive Descriptor Done */
205 /** num of bytes in the current packet being drained from rxDataFifo */
207 /** number of bytes in the rxFifo */
209 /** halt the rx state machine after current packet */
211 /** ptr to the next byte in current fragment */
213 /** count of bytes remaining in the current descriptor */
231 void rxDmaReadCopy();
232 void rxDmaWriteCopy();
239 void txDmaReadCopy();
240 void txDmaWriteCopy();
242 void rxDmaReadDone();
243 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
244 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
246 void rxDmaWriteDone();
247 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
248 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
250 void txDmaReadDone();
251 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
252 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
254 void txDmaWriteDone();
255 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
256 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
272 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
273 friend class RxKickEvent;
277 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
278 friend class TxKickEvent;
284 typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
285 friend class TxEvent;
292 * receive address filter
295 bool rxFilter(PacketPtr packet);
296 bool acceptBroadcast;
297 bool acceptMulticast;
302 PhysicalMemory *physmem;
305 * Interrupt management
307 IntrControl *intctrl;
308 void devIntrPost(uint32_t interrupts);
309 void devIntrClear(uint32_t interrupts);
310 void devIntrChangeMask();
315 void cpuIntrPost(Tick when);
319 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
320 friend class IntrEvent;
321 IntrEvent *intrEvent;
324 * Hardware checksum support
326 bool udpChecksum(PacketPtr packet, bool gen);
327 bool tcpChecksum(PacketPtr packet, bool gen);
328 bool ipChecksum(PacketPtr packet, bool gen);
329 uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
331 NSGigEInt *interface;
334 NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
335 PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
336 MemoryController *mmu, HierParams *hier, Bus *header_bus,
337 Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
338 bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
339 Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
340 PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
341 uint32_t func, bool rx_filter, const int eaddr[6]);
344 virtual void WriteConfig(int offset, int size, uint32_t data);
345 virtual void ReadConfig(int offset, int size, uint8_t *data);
347 virtual Fault read(MemReqPtr &req, uint8_t *data);
348 virtual Fault write(MemReqPtr &req, const uint8_t *data);
350 bool cpuIntrPending() const;
351 void cpuIntrAck() { cpuIntrClear(); }
353 bool recvPacket(PacketPtr packet);
356 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
358 virtual void serialize(std::ostream &os);
359 virtual void unserialize(Checkpoint *cp, const std::string §ion);
365 Stats::Scalar<> txBytes;
366 Stats::Scalar<> rxBytes;
367 Stats::Scalar<> txPackets;
368 Stats::Scalar<> rxPackets;
369 Stats::Formula txBandwidth;
370 Stats::Formula rxBandwidth;
371 Stats::Formula txPacketRate;
372 Stats::Formula rxPacketRate;
378 Tick cacheAccess(MemReqPtr &req);
382 * Ethernet Interface for an Ethernet Device
384 class NSGigEInt : public EtherInt
390 NSGigEInt(const std::string &name, NSGigE *d)
391 : EtherInt(name), dev(d) { dev->setInterface(this); }
393 virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
394 virtual void sendDone() { dev->transferDone(); }
397 #endif // __NS_GIGE_HH__