dev/ns_gige.hh

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Device module for modelling the National Semiconductor
  31  * DP83820 ethernet controller
  32  */
  33
  34 #ifndef __NS_GIGE_HH__
  35 #define __NS_GIGE_HH__
  36
  37 //#include "base/range.hh"
  38 #include "dev/etherint.hh"
  39 #include "dev/etherpkt.hh"
  40 #include "sim/eventq.hh"
  41 #include "dev/ns_gige_reg.h"
  42 #include "base/statistics.hh"
  43 #include "dev/pcidev.hh"
  44 #include "dev/tsunami.hh"
  45 #include "dev/io_device.hh"
  46 #include "mem/bus/bus.hh"
  47
  48 /** defined by the NS83820 data sheet */
  49 #define MAX_TX_FIFO_SIZE 8192
  50 #define MAX_RX_FIFO_SIZE 32768
  51
  52 /** length of ethernet address in bytes */
  53 #define EADDR_LEN 6
  54
  55 /**
  56  * Ethernet device registers
  57  */
  58 struct dp_regs {
  59     uint32_t    command;
  60     uint32_t    config;
  61     uint32_t    mear;
  62     uint32_t    ptscr;
  63     uint32_t    isr;
  64     uint32_t    imr;
  65     uint32_t    ier;
  66     uint32_t    ihr;
  67     uint32_t    txdp;
  68     uint32_t    txdp_hi;
  69     uint32_t    txcfg;
  70     uint32_t    gpior;
  71     uint32_t    rxdp;
  72     uint32_t    rxdp_hi;
  73     uint32_t    rxcfg;
  74     uint32_t    pqcr;
  75     uint32_t    wcsr;
  76     uint32_t    pcr;
  77     uint32_t    rfcr;
  78     uint32_t    rfdr;
  79     uint32_t    srr;
  80     uint32_t    mibc;
  81     uint32_t    vrcr;
  82     uint32_t    vtcr;
  83     uint32_t    vdr;
  84     uint32_t    ccsr;
  85     uint32_t    tbicr;
  86     uint32_t    tbisr;
  87     uint32_t    tanar;
  88     uint32_t    tanlpar;
  89     uint32_t    taner;
  90     uint32_t    tesr;
  91 };
  92
  93 struct dp_rom {
  94     /** for perfect match memory.  the linux driver doesn't use any other ROM */
  95     uint8_t perfectMatch[EADDR_LEN];
  96 };
  97
  98 class IntrControl;
  99 class NSGigEInt;
 100 class PhysicalMemory;
 101 class BaseInterface;
 102 class HierParams;
 103 class Bus;
 104 class PciConfigAll;
 105
 106 /**
 107  * NS DP82830 Ethernet device model
 108  */
 109 class NSGigE : public PciDev
 110 {
 111   public:
 112     /** Transmit State Machine states */
 113     enum TxState
 114     {
 115         txIdle,
 116         txDescRefr,
 117         txDescRead,
 118         txFifoBlock,
 119         txFragRead,
 120         txDescWrite,
 121         txAdvance
 122     };
 123
 124     /** Receive State Machine States */
 125     enum RxState
 126     {
 127         rxIdle,
 128         rxDescRefr,
 129         rxDescRead,
 130         rxFifoBlock,
 131         rxFragWrite,
 132         rxDescWrite,
 133         rxAdvance
 134     };
 135
 136     enum DmaState
 137     {
 138         dmaIdle,
 139         dmaReading,
 140         dmaWriting,
 141         dmaReadWaiting,
 142         dmaWriteWaiting
 143     };
 144
 145   private:
 146     /** pointer to the chipset */
 147     Tsunami *tsunami;
 148
 149   private:
 150     Addr addr;
 151     static const Addr size = sizeof(dp_regs);
 152
 153   protected:
 154     typedef std::deque<PacketPtr> pktbuf_t;
 155     typedef pktbuf_t::iterator pktiter_t;
 156
 157     /** device register file */
 158     dp_regs regs;
 159     dp_rom rom;
 160
 161     /** pci settings */
 162     bool io_enable;
 163 #if 0
 164     bool mem_enable;
 165     bool bm_enable;
 166 #endif
 167
 168     /*** BASIC STRUCTURES FOR TX/RX ***/
 169     /* Data FIFOs */
 170     pktbuf_t txFifo;
 171     pktbuf_t rxFifo;
 172
 173     /** various helper vars */
 174     PacketPtr txPacket;
 175     PacketPtr rxPacket;
 176     uint8_t *txPacketBufPtr;
 177     uint8_t *rxPacketBufPtr;
 178     uint32_t txXferLen;
 179     uint32_t rxXferLen;
 180     uint32_t txPktXmitted;
 181     bool rxDmaFree;
 182     bool txDmaFree;
 183
 184     /** DescCaches */
 185     ns_desc txDescCache;
 186     ns_desc rxDescCache;
 187
 188     /* tx State Machine */
 189     TxState txState;
 190     /** Current Transmit Descriptor Done */
 191     bool CTDD;
 192     /** amt of data in the txDataFifo in bytes (logical) */
 193     uint32_t txFifoCnt;
 194     /** current amt of free space in txDataFifo in bytes */
 195     uint32_t txFifoAvail;
 196     /** halt the tx state machine after next packet */
 197     bool txHalt;
 198     /** ptr to the next byte in the current fragment */
 199     Addr txFragPtr;
 200     /** count of bytes remaining in the current descriptor */
 201     uint32_t txDescCnt;
 202     DmaState txDmaState;
 203
 204     /** rx State Machine */
 205     RxState rxState;
 206     /** Current Receive Descriptor Done */
 207     bool CRDD;
 208     /** num of bytes in the current packet being drained from rxDataFifo */
 209     uint32_t rxPktBytes;
 210     /** number of bytes in the rxFifo */
 211     uint32_t rxFifoCnt;
 212     /** halt the rx state machine after current packet */
 213     bool rxHalt;
 214     /** ptr to the next byte in current fragment */
 215     Addr rxFragPtr;
 216     /** count of bytes remaining in the current descriptor */
 217     uint32_t rxDescCnt;
 218     DmaState rxDmaState;
 219
 220     bool extstsEnable;
 221
 222   protected:
 223     Tick dmaReadDelay;
 224     Tick dmaWriteDelay;
 225
 226     Tick dmaReadFactor;
 227     Tick dmaWriteFactor;
 228
 229     void *rxDmaData;
 230     Addr  rxDmaAddr;
 231     int   rxDmaLen;
 232     bool  doRxDmaRead();
 233     bool  doRxDmaWrite();
 234     void  rxDmaReadCopy();
 235     void  rxDmaWriteCopy();
 236
 237     void *txDmaData;
 238     Addr  txDmaAddr;
 239     int   txDmaLen;
 240     bool  doTxDmaRead();
 241     bool  doTxDmaWrite();
 242     void  txDmaReadCopy();
 243     void  txDmaWriteCopy();
 244
 245     void rxDmaReadDone();
 246     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
 247     EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 248
 249     void rxDmaWriteDone();
 250     friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
 251     EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 252
 253     void txDmaReadDone();
 254     friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
 255     EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 256
 257     void txDmaWriteDone();
 258     friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
 259     EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 260
 261     bool dmaDescFree;
 262     bool dmaDataFree;
 263
 264
 265   protected:
 266     Tick txDelay;
 267     Tick rxDelay;
 268
 269     void txReset();
 270     void rxReset();
 271     void regsReset();
 272
 273     void rxKick();
 274     Tick rxKickTick;
 275     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
 276     friend class RxKickEvent;
 277
 278     void txKick();
 279     Tick txKickTick;
 280     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
 281     friend class TxKickEvent;
 282
 283     /**
 284      * Retransmit event
 285      */
 286     void transmit();
 287     typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
 288     friend class TxEvent;
 289     TxEvent txEvent;
 290
 291     void txDump() const;
 292     void rxDump() const;
 293
 294     /**
 295      * receive address filter
 296      */
 297     bool rxFilterEnable;
 298     bool rxFilter(PacketPtr packet);
 299     bool acceptBroadcast;
 300     bool acceptMulticast;
 301     bool acceptUnicast;
 302     bool acceptPerfect;
 303     bool acceptArp;
 304
 305     PhysicalMemory *physmem;
 306
 307     /**
 308      * Interrupt management
 309      */
 310     IntrControl *intctrl;
 311     void devIntrPost(uint32_t interrupts);
 312     void devIntrClear(uint32_t interrupts);
 313     void devIntrChangeMask();
 314
 315     Tick intrDelay;
 316     Tick intrTick;
 317     bool cpuPendingIntr;
 318     void cpuIntrPost(Tick when);
 319     void cpuInterrupt();
 320     void cpuIntrClear();
 321
 322     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
 323     friend class IntrEvent;
 324     IntrEvent *intrEvent;
 325
 326     /**
 327      * Hardware checksum support
 328      */
 329     bool udpChecksum(PacketPtr packet, bool gen);
 330     bool tcpChecksum(PacketPtr packet, bool gen);
 331     bool ipChecksum(PacketPtr packet, bool gen);
 332     uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
 333
 334     NSGigEInt *interface;
 335
 336   public:
 337     NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
 338              PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
 339              MemoryController *mmu, HierParams *hier, Bus *header_bus,
 340              Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
 341              bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
 342              Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
 343              PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
 344              uint32_t func, bool rx_filter, const int eaddr[6]);
 345     ~NSGigE();
 346
 347     virtual void WriteConfig(int offset, int size, uint32_t data);
 348     virtual void ReadConfig(int offset, int size, uint8_t *data);
 349
 350     virtual Fault read(MemReqPtr &req, uint8_t *data);
 351     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 352
 353     bool cpuIntrPending() const;
 354     void cpuIntrAck() { cpuIntrClear(); }
 355
 356     bool recvPacket(PacketPtr packet);
 357     void transferDone();
 358
 359     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 360
 361     virtual void serialize(std::ostream &os);
 362     virtual void unserialize(Checkpoint *cp, const std::string &section);
 363
 364   public:
 365     void regStats();
 366
 367   private:
 368     Stats::Scalar<> txBytes;
 369     Stats::Scalar<> rxBytes;
 370     Stats::Scalar<> txPackets;
 371     Stats::Scalar<> rxPackets;
 372     Stats::Formula txBandwidth;
 373     Stats::Formula rxBandwidth;
 374     Stats::Formula txPacketRate;
 375     Stats::Formula rxPacketRate;
 376
 377   private:
 378     Tick pioLatency;
 379
 380   public:
 381     Tick cacheAccess(MemReqPtr &req);
 382 };
 383
 384 /*
 385  * Ethernet Interface for an Ethernet Device
 386  */
 387 class NSGigEInt : public EtherInt
 388 {
 389   private:
 390     NSGigE *dev;
 391
 392   public:
 393     NSGigEInt(const std::string &name, NSGigE *d)
 394         : EtherInt(name), dev(d) { dev->setInterface(this); }
 395
 396     virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
 397     virtual void sendDone() { dev->transferDone(); }
 398 };
 399
 400 #endif // __NS_GIGE_HH__