2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __DEV_NS_GIGE_HH__
35 #define __DEV_NS_GIGE_HH__
37 #include "base/inet.hh"
38 #include "base/statistics.hh"
39 #include "dev/etherint.hh"
40 #include "dev/etherpkt.hh"
41 #include "dev/io_device.hh"
42 #include "dev/ns_gige_reg.h"
43 #include "dev/pcidev.hh"
44 #include "dev/pktfifo.hh"
45 #include "mem/bus/bus.hh"
46 #include "sim/eventq.hh"
49 * Ethernet device registers
88 * for perfect match memory.
89 * the linux driver doesn't use any other ROM
91 uint8_t perfectMatch[ETH_ADDR_LEN];
102 * NS DP82830 Ethernet device model
104 class NSGigE : public PciDev
107 /** Transmit State Machine states */
119 /** Receive State Machine States */
142 static const Addr size = sizeof(dp_regs);
145 typedef std::deque<PacketPtr> pktbuf_t;
146 typedef pktbuf_t::iterator pktiter_t;
148 /** device register file */
159 /*** BASIC STRUCTURES FOR TX/RX ***/
164 /** various helper vars */
167 uint8_t *txPacketBufPtr;
168 uint8_t *rxPacketBufPtr;
178 /* tx State Machine */
182 /** Current Transmit Descriptor Done */
184 /** halt the tx state machine after next packet */
186 /** ptr to the next byte in the current fragment */
188 /** count of bytes remaining in the current descriptor */
192 /** rx State Machine */
196 /** Current Receive Descriptor Done */
198 /** num of bytes in the current packet being drained from rxDataFifo */
200 /** halt the rx state machine after current packet */
202 /** ptr to the next byte in current fragment */
204 /** count of bytes remaining in the current descriptor */
222 void rxDmaReadCopy();
223 void rxDmaWriteCopy();
230 void txDmaReadCopy();
231 void txDmaWriteCopy();
233 void rxDmaReadDone();
234 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
235 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
237 void rxDmaWriteDone();
238 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
239 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
241 void txDmaReadDone();
242 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
243 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
245 void txDmaWriteDone();
246 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
247 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
263 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
264 friend void RxKickEvent::process();
268 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
269 friend void TxKickEvent::process();
275 void txEventTransmit()
278 if (txState == txFifoBlock)
281 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
282 friend void TxEvent::process();
289 * receive address filter
292 bool rxFilter(const PacketPtr &packet);
293 bool acceptBroadcast;
294 bool acceptMulticast;
299 PhysicalMemory *physmem;
302 * Interrupt management
304 void devIntrPost(uint32_t interrupts);
305 void devIntrClear(uint32_t interrupts);
306 void devIntrChangeMask();
311 void cpuIntrPost(Tick when);
315 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
316 friend void IntrEvent::process();
317 IntrEvent *intrEvent;
318 NSGigEInt *interface;
321 struct Params : public PciDev::Params
323 PhysicalMemory *pmem;
334 Tick dma_write_delay;
335 Tick dma_read_factor;
336 Tick dma_write_factor;
339 uint32_t tx_fifo_size;
340 uint32_t rx_fifo_size;
343 NSGigE(Params *params);
345 const Params *params() const { return (const Params *)_params; }
347 virtual void WriteConfig(int offset, int size, uint32_t data);
348 virtual void ReadConfig(int offset, int size, uint8_t *data);
350 virtual Fault read(MemReqPtr &req, uint8_t *data);
351 virtual Fault write(MemReqPtr &req, const uint8_t *data);
353 bool cpuIntrPending() const;
354 void cpuIntrAck() { cpuIntrClear(); }
356 bool recvPacket(PacketPtr packet);
359 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
361 virtual void serialize(std::ostream &os);
362 virtual void unserialize(Checkpoint *cp, const std::string §ion);
368 Stats::Scalar<> txBytes;
369 Stats::Scalar<> rxBytes;
370 Stats::Scalar<> txPackets;
371 Stats::Scalar<> rxPackets;
372 Stats::Scalar<> txIpChecksums;
373 Stats::Scalar<> rxIpChecksums;
374 Stats::Scalar<> txTcpChecksums;
375 Stats::Scalar<> rxTcpChecksums;
376 Stats::Scalar<> txUdpChecksums;
377 Stats::Scalar<> rxUdpChecksums;
378 Stats::Scalar<> descDmaReads;
379 Stats::Scalar<> descDmaWrites;
380 Stats::Scalar<> descDmaRdBytes;
381 Stats::Scalar<> descDmaWrBytes;
382 Stats::Formula totBandwidth;
383 Stats::Formula totPackets;
384 Stats::Formula totBytes;
385 Stats::Formula totPacketRate;
386 Stats::Formula txBandwidth;
387 Stats::Formula rxBandwidth;
388 Stats::Formula txPacketRate;
389 Stats::Formula rxPacketRate;
390 Stats::Scalar<> postedSwi;
391 Stats::Formula coalescedSwi;
392 Stats::Scalar<> totalSwi;
393 Stats::Scalar<> postedRxIdle;
394 Stats::Formula coalescedRxIdle;
395 Stats::Scalar<> totalRxIdle;
396 Stats::Scalar<> postedRxOk;
397 Stats::Formula coalescedRxOk;
398 Stats::Scalar<> totalRxOk;
399 Stats::Scalar<> postedRxDesc;
400 Stats::Formula coalescedRxDesc;
401 Stats::Scalar<> totalRxDesc;
402 Stats::Scalar<> postedTxOk;
403 Stats::Formula coalescedTxOk;
404 Stats::Scalar<> totalTxOk;
405 Stats::Scalar<> postedTxIdle;
406 Stats::Formula coalescedTxIdle;
407 Stats::Scalar<> totalTxIdle;
408 Stats::Scalar<> postedTxDesc;
409 Stats::Formula coalescedTxDesc;
410 Stats::Scalar<> totalTxDesc;
411 Stats::Scalar<> postedRxOrn;
412 Stats::Formula coalescedRxOrn;
413 Stats::Scalar<> totalRxOrn;
414 Stats::Formula coalescedTotal;
415 Stats::Scalar<> postedInterrupts;
416 Stats::Scalar<> droppedPackets;
419 Tick cacheAccess(MemReqPtr &req);
423 * Ethernet Interface for an Ethernet Device
425 class NSGigEInt : public EtherInt
431 NSGigEInt(const std::string &name, NSGigE *d)
432 : EtherInt(name), dev(d) { dev->setInterface(this); }
434 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
435 virtual void sendDone() { dev->transferDone(); }
438 #endif // __DEV_NS_GIGE_HH__