dev/ns_gige.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Device module for modelling the National Semiconductor
  31  * DP83820 ethernet controller
  32  */
  33
  34 #ifndef __DEV_NS_GIGE_HH__
  35 #define __DEV_NS_GIGE_HH__
  36
  37 #include "base/inet.hh"
  38 #include "base/statistics.hh"
  39 #include "dev/etherint.hh"
  40 #include "dev/etherpkt.hh"
  41 #include "dev/io_device.hh"
  42 #include "dev/ns_gige_reg.h"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pktfifo.hh"
  45 #include "mem/bus/bus.hh"
  46 #include "sim/eventq.hh"
  47
  48 // Hash filtering constants
  49 const uint16_t FHASH_ADDR  = 0x100;
  50 const uint16_t FHASH_SIZE  = 0x100;
  51
  52 // EEPROM constants
  53 const uint8_t  EEPROM_READ = 0x2;
  54 const uint8_t  EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
  55 const uint8_t  EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
  56 const uint8_t  EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
  57 const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
  58
  59 /**
  60  * Ethernet device registers
  61  */
  62 struct dp_regs {
  63     uint32_t    command;
  64     uint32_t    config;
  65     uint32_t    mear;
  66     uint32_t    ptscr;
  67     uint32_t    isr;
  68     uint32_t    imr;
  69     uint32_t    ier;
  70     uint32_t    ihr;
  71     uint32_t    txdp;
  72     uint32_t    txdp_hi;
  73     uint32_t    txcfg;
  74     uint32_t    gpior;
  75     uint32_t    rxdp;
  76     uint32_t    rxdp_hi;
  77     uint32_t    rxcfg;
  78     uint32_t    pqcr;
  79     uint32_t    wcsr;
  80     uint32_t    pcr;
  81     uint32_t    rfcr;
  82     uint32_t    rfdr;
  83     uint32_t    brar;
  84     uint32_t    brdr;
  85     uint32_t    srr;
  86     uint32_t    mibc;
  87     uint32_t    vrcr;
  88     uint32_t    vtcr;
  89     uint32_t    vdr;
  90     uint32_t    ccsr;
  91     uint32_t    tbicr;
  92     uint32_t    tbisr;
  93     uint32_t    tanar;
  94     uint32_t    tanlpar;
  95     uint32_t    taner;
  96     uint32_t    tesr;
  97 };
  98
  99 struct dp_rom {
 100     /**
 101      * for perfect match memory.
 102      * the linux driver doesn't use any other ROM
 103      */
 104     uint8_t perfectMatch[ETH_ADDR_LEN];
 105
 106     /**
 107      * for hash table memory.
 108      * used by the freebsd driver
 109      */
 110     uint8_t filterHash[FHASH_SIZE];
 111 };
 112
 113 class NSGigEInt;
 114 class PhysicalMemory;
 115 class BaseInterface;
 116 class HierParams;
 117 class Bus;
 118 class PciConfigAll;
 119
 120 /**
 121  * NS DP83820 Ethernet device model
 122  */
 123 class NSGigE : public PciDev
 124 {
 125   public:
 126     /** Transmit State Machine states */
 127     enum TxState
 128     {
 129         txIdle,
 130         txDescRefr,
 131         txDescRead,
 132         txFifoBlock,
 133         txFragRead,
 134         txDescWrite,
 135         txAdvance
 136     };
 137
 138     /** Receive State Machine States */
 139     enum RxState
 140     {
 141         rxIdle,
 142         rxDescRefr,
 143         rxDescRead,
 144         rxFifoBlock,
 145         rxFragWrite,
 146         rxDescWrite,
 147         rxAdvance
 148     };
 149
 150     enum DmaState
 151     {
 152         dmaIdle,
 153         dmaReading,
 154         dmaWriting,
 155         dmaReadWaiting,
 156         dmaWriteWaiting
 157     };
 158
 159     /** EEPROM State Machine States */
 160     enum EEPROMState
 161     {
 162         eepromStart,
 163         eepromGetOpcode,
 164         eepromGetAddress,
 165         eepromRead
 166     };
 167
 168   private:
 169     Addr addr;
 170     static const Addr size = sizeof(dp_regs);
 171
 172   protected:
 173     /** device register file */
 174     dp_regs regs;
 175     dp_rom rom;
 176
 177     /** pci settings */
 178     bool ioEnable;
 179 #if 0
 180     bool memEnable;
 181     bool bmEnable;
 182 #endif
 183
 184     /*** BASIC STRUCTURES FOR TX/RX ***/
 185     /* Data FIFOs */
 186     PacketFifo txFifo;
 187     PacketFifo rxFifo;
 188
 189     /** various helper vars */
 190     PacketPtr txPacket;
 191     PacketPtr rxPacket;
 192     uint8_t *txPacketBufPtr;
 193     uint8_t *rxPacketBufPtr;
 194     uint32_t txXferLen;
 195     uint32_t rxXferLen;
 196     bool rxDmaFree;
 197     bool txDmaFree;
 198
 199     /** DescCaches */
 200     ns_desc32 txDesc32;
 201     ns_desc32 rxDesc32;
 202     ns_desc64 txDesc64;
 203     ns_desc64 rxDesc64;
 204
 205     /* state machine cycle time */
 206     Tick clock;
 207     inline Tick cycles(int numCycles) const { return numCycles * clock; }
 208
 209     /* tx State Machine */
 210     TxState txState;
 211     bool txEnable;
 212
 213     /** Current Transmit Descriptor Done */
 214     bool CTDD;
 215     /** halt the tx state machine after next packet */
 216     bool txHalt;
 217     /** ptr to the next byte in the current fragment */
 218     Addr txFragPtr;
 219     /** count of bytes remaining in the current descriptor */
 220     uint32_t txDescCnt;
 221     DmaState txDmaState;
 222
 223     /** rx State Machine */
 224     RxState rxState;
 225     bool rxEnable;
 226
 227     /** Current Receive Descriptor Done */
 228     bool CRDD;
 229     /** num of bytes in the current packet being drained from rxDataFifo */
 230     uint32_t rxPktBytes;
 231     /** halt the rx state machine after current packet */
 232     bool rxHalt;
 233     /** ptr to the next byte in current fragment */
 234     Addr rxFragPtr;
 235     /** count of bytes remaining in the current descriptor */
 236     uint32_t rxDescCnt;
 237     DmaState rxDmaState;
 238
 239     bool extstsEnable;
 240
 241     /** EEPROM State Machine */
 242     EEPROMState eepromState;
 243     bool eepromClk;
 244     uint8_t eepromBitsToRx;
 245     uint8_t eepromOpcode;
 246     uint8_t eepromAddress;
 247     uint16_t eepromData;
 248
 249   protected:
 250     Tick dmaReadDelay;
 251     Tick dmaWriteDelay;
 252
 253     Tick dmaReadFactor;
 254     Tick dmaWriteFactor;
 255
 256     void *rxDmaData;
 257     Addr  rxDmaAddr;
 258     int   rxDmaLen;
 259     bool  doRxDmaRead();
 260     bool  doRxDmaWrite();
 261     void  rxDmaReadCopy();
 262     void  rxDmaWriteCopy();
 263
 264     void *txDmaData;
 265     Addr  txDmaAddr;
 266     int   txDmaLen;
 267     bool  doTxDmaRead();
 268     bool  doTxDmaWrite();
 269     void  txDmaReadCopy();
 270     void  txDmaWriteCopy();
 271
 272     void rxDmaReadDone();
 273     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
 274     EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 275
 276     void rxDmaWriteDone();
 277     friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
 278     EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 279
 280     void txDmaReadDone();
 281     friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
 282     EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 283
 284     void txDmaWriteDone();
 285     friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
 286     EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 287
 288     bool dmaDescFree;
 289     bool dmaDataFree;
 290
 291   protected:
 292     Tick txDelay;
 293     Tick rxDelay;
 294
 295     void txReset();
 296     void rxReset();
 297     void regsReset();
 298
 299     void rxKick();
 300     Tick rxKickTick;
 301     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
 302     friend void RxKickEvent::process();
 303     RxKickEvent rxKickEvent;
 304
 305     void txKick();
 306     Tick txKickTick;
 307     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
 308     friend void TxKickEvent::process();
 309     TxKickEvent txKickEvent;
 310
 311     void eepromKick();
 312
 313     /**
 314      * Retransmit event
 315      */
 316     void transmit();
 317     void txEventTransmit()
 318     {
 319         transmit();
 320         if (txState == txFifoBlock)
 321             txKick();
 322     }
 323     typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
 324     friend void TxEvent::process();
 325     TxEvent txEvent;
 326
 327     void txDump() const;
 328     void rxDump() const;
 329
 330     /**
 331      * receive address filter
 332      */
 333     bool rxFilterEnable;
 334     bool rxFilter(const PacketPtr &packet);
 335     bool acceptBroadcast;
 336     bool acceptMulticast;
 337     bool acceptUnicast;
 338     bool acceptPerfect;
 339     bool acceptArp;
 340     bool multicastHashEnable;
 341
 342     PhysicalMemory *physmem;
 343
 344     /**
 345      * Interrupt management
 346      */
 347     void devIntrPost(uint32_t interrupts);
 348     void devIntrClear(uint32_t interrupts);
 349     void devIntrChangeMask();
 350
 351     Tick intrDelay;
 352     Tick intrTick;
 353     bool cpuPendingIntr;
 354     void cpuIntrPost(Tick when);
 355     void cpuInterrupt();
 356     void cpuIntrClear();
 357
 358     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
 359     friend void IntrEvent::process();
 360     IntrEvent *intrEvent;
 361     NSGigEInt *interface;
 362
 363   public:
 364     struct Params : public PciDev::Params
 365     {
 366         PhysicalMemory *pmem;
 367         HierParams *hier;
 368         Bus *pio_bus;
 369         Bus *header_bus;
 370         Bus *payload_bus;
 371         Tick clock;
 372         Tick intr_delay;
 373         Tick tx_delay;
 374         Tick rx_delay;
 375         Tick pio_latency;
 376         bool dma_desc_free;
 377         bool dma_data_free;
 378         Tick dma_read_delay;
 379         Tick dma_write_delay;
 380         Tick dma_read_factor;
 381         Tick dma_write_factor;
 382         bool rx_filter;
 383         Net::EthAddr eaddr;
 384         uint32_t tx_fifo_size;
 385         uint32_t rx_fifo_size;
 386         bool rx_thread;
 387         bool tx_thread;
 388         bool rss;
 389         bool dma_no_allocate;
 390     };
 391
 392     NSGigE(Params *params);
 393     ~NSGigE();
 394     const Params *params() const { return (const Params *)_params; }
 395
 396     virtual void writeConfig(int offset, int size, const uint8_t *data);
 397     virtual void readConfig(int offset, int size, uint8_t *data);
 398
 399     virtual Fault read(MemReqPtr &req, uint8_t *data);
 400     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 401
 402     bool cpuIntrPending() const;
 403     void cpuIntrAck() { cpuIntrClear(); }
 404
 405     bool recvPacket(PacketPtr packet);
 406     void transferDone();
 407
 408     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 409
 410     virtual void serialize(std::ostream &os);
 411     virtual void unserialize(Checkpoint *cp, const std::string &section);
 412
 413   public:
 414     void regStats();
 415
 416   private:
 417     Stats::Scalar<> txBytes;
 418     Stats::Scalar<> rxBytes;
 419     Stats::Scalar<> txPackets;
 420     Stats::Scalar<> rxPackets;
 421     Stats::Scalar<> txIpChecksums;
 422     Stats::Scalar<> rxIpChecksums;
 423     Stats::Scalar<> txTcpChecksums;
 424     Stats::Scalar<> rxTcpChecksums;
 425     Stats::Scalar<> txUdpChecksums;
 426     Stats::Scalar<> rxUdpChecksums;
 427     Stats::Scalar<> descDmaReads;
 428     Stats::Scalar<> descDmaWrites;
 429     Stats::Scalar<> descDmaRdBytes;
 430     Stats::Scalar<> descDmaWrBytes;
 431     Stats::Formula totBandwidth;
 432     Stats::Formula totPackets;
 433     Stats::Formula totBytes;
 434     Stats::Formula totPacketRate;
 435     Stats::Formula txBandwidth;
 436     Stats::Formula rxBandwidth;
 437     Stats::Formula txPacketRate;
 438     Stats::Formula rxPacketRate;
 439     Stats::Scalar<> postedSwi;
 440     Stats::Formula coalescedSwi;
 441     Stats::Scalar<> totalSwi;
 442     Stats::Scalar<> postedRxIdle;
 443     Stats::Formula coalescedRxIdle;
 444     Stats::Scalar<> totalRxIdle;
 445     Stats::Scalar<> postedRxOk;
 446     Stats::Formula coalescedRxOk;
 447     Stats::Scalar<> totalRxOk;
 448     Stats::Scalar<> postedRxDesc;
 449     Stats::Formula coalescedRxDesc;
 450     Stats::Scalar<> totalRxDesc;
 451     Stats::Scalar<> postedTxOk;
 452     Stats::Formula coalescedTxOk;
 453     Stats::Scalar<> totalTxOk;
 454     Stats::Scalar<> postedTxIdle;
 455     Stats::Formula coalescedTxIdle;
 456     Stats::Scalar<> totalTxIdle;
 457     Stats::Scalar<> postedTxDesc;
 458     Stats::Formula coalescedTxDesc;
 459     Stats::Scalar<> totalTxDesc;
 460     Stats::Scalar<> postedRxOrn;
 461     Stats::Formula coalescedRxOrn;
 462     Stats::Scalar<> totalRxOrn;
 463     Stats::Formula coalescedTotal;
 464     Stats::Scalar<> postedInterrupts;
 465     Stats::Scalar<> droppedPackets;
 466
 467   public:
 468     Tick cacheAccess(MemReqPtr &req);
 469 };
 470
 471 /*
 472  * Ethernet Interface for an Ethernet Device
 473  */
 474 class NSGigEInt : public EtherInt
 475 {
 476   private:
 477     NSGigE *dev;
 478
 479   public:
 480     NSGigEInt(const std::string &name, NSGigE *d)
 481         : EtherInt(name), dev(d) { dev->setInterface(this); }
 482
 483     virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
 484     virtual void sendDone() { dev->transferDone(); }
 485 };
 486
 487 #endif // __DEV_NS_GIGE_HH__