2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __NS_GIGE_HH__
35 #define __NS_GIGE_HH__
37 #include "base/statistics.hh"
38 #include "dev/etherint.hh"
39 #include "dev/etherpkt.hh"
40 #include "dev/io_device.hh"
41 #include "dev/ns_gige_reg.h"
42 #include "dev/pcidev.hh"
43 #include "dev/tsunami.hh"
44 #include "mem/bus/bus.hh"
45 #include "sim/eventq.hh"
47 /** length of ethernet address in bytes */
51 * Ethernet device registers
90 * for perfect match memory.
91 * the linux driver doesn't use any other ROM
93 uint8_t perfectMatch[EADDR_LEN];
105 * NS DP82830 Ethernet device model
107 class NSGigE : public PciDev
110 /** Transmit State Machine states */
122 /** Receive State Machine States */
144 /** pointer to the chipset */
149 static const Addr size = sizeof(dp_regs);
152 typedef std::deque<PacketPtr> pktbuf_t;
153 typedef pktbuf_t::iterator pktiter_t;
155 /** device register file */
166 /*** BASIC STRUCTURES FOR TX/RX ***/
169 uint32_t maxTxFifoSize;
171 uint32_t maxRxFifoSize;
173 /** various helper vars */
176 uint8_t *txPacketBufPtr;
177 uint8_t *rxPacketBufPtr;
187 /* tx State Machine */
189 /** Current Transmit Descriptor Done */
191 /** current amt of free space in txDataFifo in bytes */
192 uint32_t txFifoAvail;
193 /** halt the tx state machine after next packet */
195 /** ptr to the next byte in the current fragment */
197 /** count of bytes remaining in the current descriptor */
201 /** rx State Machine */
203 /** Current Receive Descriptor Done */
205 /** num of bytes in the current packet being drained from rxDataFifo */
207 /** number of bytes in the rxFifo */
209 /** halt the rx state machine after current packet */
211 /** ptr to the next byte in current fragment */
213 /** count of bytes remaining in the current descriptor */
231 void rxDmaReadCopy();
232 void rxDmaWriteCopy();
239 void txDmaReadCopy();
240 void txDmaWriteCopy();
242 void rxDmaReadDone();
243 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
244 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
246 void rxDmaWriteDone();
247 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
248 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
250 void txDmaReadDone();
251 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
252 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
254 void txDmaWriteDone();
255 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
256 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
272 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
273 friend class RxKickEvent;
277 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
278 friend class TxKickEvent;
284 void txEventTransmit()
287 if (txState == txFifoBlock)
290 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
291 friend class TxEvent;
298 * receive address filter
301 bool rxFilter(PacketPtr packet);
302 bool acceptBroadcast;
303 bool acceptMulticast;
308 PhysicalMemory *physmem;
311 * Interrupt management
313 IntrControl *intctrl;
314 void devIntrPost(uint32_t interrupts);
315 void devIntrClear(uint32_t interrupts);
316 void devIntrChangeMask();
321 void cpuIntrPost(Tick when);
325 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
326 friend class IntrEvent;
327 IntrEvent *intrEvent;
330 * Hardware checksum support
332 bool udpChecksum(PacketPtr packet, bool gen);
333 bool tcpChecksum(PacketPtr packet, bool gen);
334 bool ipChecksum(PacketPtr packet, bool gen);
335 uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
337 NSGigEInt *interface;
340 NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
341 PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
342 MemoryController *mmu, HierParams *hier, Bus *header_bus,
343 Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
344 bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
345 Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
346 PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
347 uint32_t func, bool rx_filter, const int eaddr[6],
348 uint32_t tx_fifo_size, uint32_t rx_fifo_size);
351 virtual void WriteConfig(int offset, int size, uint32_t data);
352 virtual void ReadConfig(int offset, int size, uint8_t *data);
354 virtual Fault read(MemReqPtr &req, uint8_t *data);
355 virtual Fault write(MemReqPtr &req, const uint8_t *data);
357 bool cpuIntrPending() const;
358 void cpuIntrAck() { cpuIntrClear(); }
360 bool recvPacket(PacketPtr packet);
363 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
365 virtual void serialize(std::ostream &os);
366 virtual void unserialize(Checkpoint *cp, const std::string §ion);
372 Stats::Scalar<> txBytes;
373 Stats::Scalar<> rxBytes;
374 Stats::Scalar<> txPackets;
375 Stats::Scalar<> rxPackets;
376 Stats::Scalar<> txIPChecksums;
377 Stats::Scalar<> rxIPChecksums;
378 Stats::Scalar<> txTCPChecksums;
379 Stats::Scalar<> rxTCPChecksums;
380 Stats::Scalar<> descDmaReads;
381 Stats::Scalar<> descDmaWrites;
382 Stats::Scalar<> descDmaRdBytes;
383 Stats::Scalar<> descDmaWrBytes;
384 Stats::Formula txBandwidth;
385 Stats::Formula rxBandwidth;
386 Stats::Formula txPacketRate;
387 Stats::Formula rxPacketRate;
390 Tick cacheAccess(MemReqPtr &req);
394 * Ethernet Interface for an Ethernet Device
396 class NSGigEInt : public EtherInt
402 NSGigEInt(const std::string &name, NSGigE *d)
403 : EtherInt(name), dev(d) { dev->setInterface(this); }
405 virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
406 virtual void sendDone() { dev->transferDone(); }
409 #endif // __NS_GIGE_HH__