2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __DEV_NS_GIGE_HH__
35 #define __DEV_NS_GIGE_HH__
37 #include "base/inet.hh"
38 #include "base/statistics.hh"
39 #include "dev/etherint.hh"
40 #include "dev/etherpkt.hh"
41 #include "dev/io_device.hh"
42 #include "dev/ns_gige_reg.h"
43 #include "dev/pcidev.hh"
44 #include "dev/pktfifo.hh"
45 #include "mem/bus/bus.hh"
46 #include "sim/eventq.hh"
48 // Hash filtering constants
49 const uint16_t FHASH_ADDR = 0x100;
50 const uint16_t FHASH_SIZE = 0x100;
53 const uint8_t EEPROM_READ = 0x2;
54 const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
55 const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
56 const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
57 const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
60 * Ethernet device registers
101 * for perfect match memory.
102 * the linux driver doesn't use any other ROM
104 uint8_t perfectMatch[ETH_ADDR_LEN];
107 * for hash table memory.
108 * used by the freebsd driver
110 uint8_t filterHash[FHASH_SIZE];
114 class PhysicalMemory;
121 * NS DP83820 Ethernet device model
123 class NSGigE : public PciDev
126 /** Transmit State Machine states */
138 /** Receive State Machine States */
159 /** EEPROM State Machine States */
170 static const Addr size = sizeof(dp_regs);
173 /** device register file */
184 /*** BASIC STRUCTURES FOR TX/RX ***/
189 /** various helper vars */
192 uint8_t *txPacketBufPtr;
193 uint8_t *rxPacketBufPtr;
205 /* state machine cycle time */
207 inline Tick cycles(int numCycles) const { return numCycles * clock; }
209 /* tx State Machine */
213 /** Current Transmit Descriptor Done */
215 /** halt the tx state machine after next packet */
217 /** ptr to the next byte in the current fragment */
219 /** count of bytes remaining in the current descriptor */
223 /** rx State Machine */
227 /** Current Receive Descriptor Done */
229 /** num of bytes in the current packet being drained from rxDataFifo */
231 /** halt the rx state machine after current packet */
233 /** ptr to the next byte in current fragment */
235 /** count of bytes remaining in the current descriptor */
241 /** EEPROM State Machine */
242 EEPROMState eepromState;
244 uint8_t eepromBitsToRx;
245 uint8_t eepromOpcode;
246 uint8_t eepromAddress;
261 void rxDmaReadCopy();
262 void rxDmaWriteCopy();
269 void txDmaReadCopy();
270 void txDmaWriteCopy();
272 void rxDmaReadDone();
273 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
274 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
276 void rxDmaWriteDone();
277 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
278 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
280 void txDmaReadDone();
281 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
282 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
284 void txDmaWriteDone();
285 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
286 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
301 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
302 friend void RxKickEvent::process();
303 RxKickEvent rxKickEvent;
307 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
308 friend void TxKickEvent::process();
309 TxKickEvent txKickEvent;
317 void txEventTransmit()
320 if (txState == txFifoBlock)
323 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
324 friend void TxEvent::process();
331 * receive address filter
334 bool rxFilter(const PacketPtr &packet);
335 bool acceptBroadcast;
336 bool acceptMulticast;
340 bool multicastHashEnable;
342 PhysicalMemory *physmem;
345 * Interrupt management
347 void devIntrPost(uint32_t interrupts);
348 void devIntrClear(uint32_t interrupts);
349 void devIntrChangeMask();
354 void cpuIntrPost(Tick when);
358 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
359 friend void IntrEvent::process();
360 IntrEvent *intrEvent;
361 NSGigEInt *interface;
364 struct Params : public PciDev::Params
366 PhysicalMemory *pmem;
379 Tick dma_write_delay;
380 Tick dma_read_factor;
381 Tick dma_write_factor;
384 uint32_t tx_fifo_size;
385 uint32_t rx_fifo_size;
388 bool dma_no_allocate;
391 NSGigE(Params *params);
393 const Params *params() const { return (const Params *)_params; }
395 virtual void writeConfig(int offset, int size, const uint8_t *data);
396 virtual void readConfig(int offset, int size, uint8_t *data);
398 virtual Fault read(MemReqPtr &req, uint8_t *data);
399 virtual Fault write(MemReqPtr &req, const uint8_t *data);
401 bool cpuIntrPending() const;
402 void cpuIntrAck() { cpuIntrClear(); }
404 bool recvPacket(PacketPtr packet);
407 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
409 virtual void serialize(std::ostream &os);
410 virtual void unserialize(Checkpoint *cp, const std::string §ion);
416 Stats::Scalar<> txBytes;
417 Stats::Scalar<> rxBytes;
418 Stats::Scalar<> txPackets;
419 Stats::Scalar<> rxPackets;
420 Stats::Scalar<> txIpChecksums;
421 Stats::Scalar<> rxIpChecksums;
422 Stats::Scalar<> txTcpChecksums;
423 Stats::Scalar<> rxTcpChecksums;
424 Stats::Scalar<> txUdpChecksums;
425 Stats::Scalar<> rxUdpChecksums;
426 Stats::Scalar<> descDmaReads;
427 Stats::Scalar<> descDmaWrites;
428 Stats::Scalar<> descDmaRdBytes;
429 Stats::Scalar<> descDmaWrBytes;
430 Stats::Formula totBandwidth;
431 Stats::Formula totPackets;
432 Stats::Formula totBytes;
433 Stats::Formula totPacketRate;
434 Stats::Formula txBandwidth;
435 Stats::Formula rxBandwidth;
436 Stats::Formula txPacketRate;
437 Stats::Formula rxPacketRate;
438 Stats::Scalar<> postedSwi;
439 Stats::Formula coalescedSwi;
440 Stats::Scalar<> totalSwi;
441 Stats::Scalar<> postedRxIdle;
442 Stats::Formula coalescedRxIdle;
443 Stats::Scalar<> totalRxIdle;
444 Stats::Scalar<> postedRxOk;
445 Stats::Formula coalescedRxOk;
446 Stats::Scalar<> totalRxOk;
447 Stats::Scalar<> postedRxDesc;
448 Stats::Formula coalescedRxDesc;
449 Stats::Scalar<> totalRxDesc;
450 Stats::Scalar<> postedTxOk;
451 Stats::Formula coalescedTxOk;
452 Stats::Scalar<> totalTxOk;
453 Stats::Scalar<> postedTxIdle;
454 Stats::Formula coalescedTxIdle;
455 Stats::Scalar<> totalTxIdle;
456 Stats::Scalar<> postedTxDesc;
457 Stats::Formula coalescedTxDesc;
458 Stats::Scalar<> totalTxDesc;
459 Stats::Scalar<> postedRxOrn;
460 Stats::Formula coalescedRxOrn;
461 Stats::Scalar<> totalRxOrn;
462 Stats::Formula coalescedTotal;
463 Stats::Scalar<> postedInterrupts;
464 Stats::Scalar<> droppedPackets;
467 Tick cacheAccess(MemReqPtr &req);
471 * Ethernet Interface for an Ethernet Device
473 class NSGigEInt : public EtherInt
479 NSGigEInt(const std::string &name, NSGigE *d)
480 : EtherInt(name), dev(d) { dev->setInterface(this); }
482 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
483 virtual void sendDone() { dev->transferDone(); }
486 #endif // __DEV_NS_GIGE_HH__