2 * Copyright (c) 2003 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __NS_GIGE_HH__
35 #define __NS_GIGE_HH__
37 //#include "base/range.hh"
38 #include "dev/etherint.hh"
39 #include "dev/etherpkt.hh"
40 #include "sim/eventq.hh"
41 #include "dev/ns_gige_reg.h"
42 #include "base/statistics.hh"
43 #include "dev/pcidev.hh"
44 #include "dev/tsunami.hh"
45 #include "dev/io_device.hh"
46 #include "mem/bus/bus.hh"
48 /** defined by the NS83820 data sheet */
49 #define MAX_TX_FIFO_SIZE 8192
50 #define MAX_RX_FIFO_SIZE 32768
52 /** length of ethernet address in bytes */
56 * Ethernet device registers
94 /** for perfect match memory. the linux driver doesn't use any other ROM */
95 uint8_t perfectMatch[EADDR_LEN];
100 class PhysicalMemory;
107 * NS DP82830 Ethernet device model
109 class NSGigE : public PciDev
112 /** Transmit State Machine states */
124 /** Receive State Machine States */
146 /** pointer to the chipset */
151 static const Addr size = sizeof(dp_regs);
154 typedef std::deque<PacketPtr> pktbuf_t;
155 typedef pktbuf_t::iterator pktiter_t;
157 /** device register file */
161 /*** BASIC STRUCTURES FOR TX/RX ***/
166 /** various helper vars */
167 uint8_t *txPacketBufPtr;
168 uint8_t *rxPacketBufPtr;
171 uint32_t txPktXmitted;
181 /* tx State Machine */
183 /** Current Transmit Descriptor Done */
185 /** amt of data in the txDataFifo in bytes (logical) */
187 /** current amt of free space in txDataFifo in bytes */
188 uint32_t txFifoAvail;
189 /** halt the tx state machine after next packet */
191 /** ptr to the next byte in the current fragment */
193 /** count of bytes remaining in the current descriptor */
197 /** rx State Machine */
199 /** Current Receive Descriptor Done */
201 /** num of bytes in the current packet being drained from rxDataFifo */
203 /** number of bytes in the rxFifo */
205 /** halt the rx state machine after current packet */
207 /** ptr to the next byte in current fragment */
209 /** count of bytes remaining in the current descriptor */
227 void rxDmaReadCopy();
228 void rxDmaWriteCopy();
235 void txDmaReadCopy();
236 void txDmaWriteCopy();
238 void rxDmaReadDone();
239 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
240 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
242 void rxDmaWriteDone();
243 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
244 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
246 void txDmaReadDone();
247 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
248 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
250 void txDmaWriteDone();
251 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
252 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
265 memset(®s, 0, sizeof(regs));
266 regs.config = 0x80000000;
268 regs.isr = 0x00608000;
279 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
280 friend class RxKickEvent;
284 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
285 friend class TxKickEvent;
291 typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
292 friend class TxEvent;
299 * receive address filter
302 bool rxFilter(PacketPtr packet);
303 bool acceptBroadcast;
304 bool acceptMulticast;
309 PhysicalMemory *physmem;
312 * Interrupt management
314 IntrControl *intctrl;
315 void devIntrPost(uint32_t interrupts);
316 void devIntrClear(uint32_t interrupts);
317 void devIntrChangeMask();
322 void cpuIntrPost(Tick when);
326 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
327 friend class IntrEvent;
328 IntrEvent *intrEvent;
331 * Hardware checksum support
333 bool udpChecksum(PacketPtr packet, bool gen);
334 bool tcpChecksum(PacketPtr packet, bool gen);
335 bool ipChecksum(PacketPtr packet, bool gen);
336 uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
338 NSGigEInt *interface;
341 NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
342 PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
343 MemoryController *mmu, HierParams *hier, Bus *header_bus,
344 Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
345 bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
346 Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
347 PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
348 uint32_t func, bool rx_filter, const int eaddr[6]);
351 virtual void WriteConfig(int offset, int size, uint32_t data);
352 virtual void ReadConfig(int offset, int size, uint8_t *data);
354 virtual Fault read(MemReqPtr &req, uint8_t *data);
355 virtual Fault write(MemReqPtr &req, const uint8_t *data);
357 bool cpuIntrPending() const;
358 void cpuIntrAck() { cpuIntrClear(); }
360 bool recvPacket(PacketPtr packet);
363 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
365 virtual void serialize(std::ostream &os);
366 virtual void unserialize(Checkpoint *cp, const std::string §ion);
372 Stats::Scalar<> txBytes;
373 Stats::Scalar<> rxBytes;
374 Stats::Scalar<> txPackets;
375 Stats::Scalar<> rxPackets;
376 Stats::Formula txBandwidth;
377 Stats::Formula rxBandwidth;
378 Stats::Formula txPacketRate;
379 Stats::Formula rxPacketRate;
385 Tick cacheAccess(MemReqPtr &req);
389 * Ethernet Interface for an Ethernet Device
391 class NSGigEInt : public EtherInt
397 NSGigEInt(const std::string &name, NSGigE *d)
398 : EtherInt(name), dev(d) { dev->setInterface(this); }
400 virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
401 virtual void sendDone() { dev->transferDone(); }
404 #endif // __NS_GIGE_HH__