2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * Device module for modelling the National Semiconductor
31 * DP83820 ethernet controller
34 #ifndef __DEV_NS_GIGE_HH__
35 #define __DEV_NS_GIGE_HH__
37 #include "base/inet.hh"
38 #include "base/statistics.hh"
39 #include "dev/etherint.hh"
40 #include "dev/etherpkt.hh"
41 #include "dev/io_device.hh"
42 #include "dev/ns_gige_reg.h"
43 #include "dev/pcidev.hh"
44 #include "dev/pktfifo.hh"
45 #include "mem/bus/bus.hh"
46 #include "sim/eventq.hh"
49 * Ethernet device registers
88 * for perfect match memory.
89 * the linux driver doesn't use any other ROM
91 uint8_t perfectMatch[ETH_ADDR_LEN];
102 * NS DP82830 Ethernet device model
104 class NSGigE : public PciDev
107 /** Transmit State Machine states */
119 /** Receive State Machine States */
142 static const Addr size = sizeof(dp_regs);
145 typedef std::deque<PacketPtr> pktbuf_t;
146 typedef pktbuf_t::iterator pktiter_t;
148 /** device register file */
159 /*** BASIC STRUCTURES FOR TX/RX ***/
164 /** various helper vars */
167 uint8_t *txPacketBufPtr;
168 uint8_t *rxPacketBufPtr;
178 /* state machine cycle time */
180 inline Tick cycles(int numCycles) const { return numCycles * clock; }
182 /* tx State Machine */
186 /** Current Transmit Descriptor Done */
188 /** halt the tx state machine after next packet */
190 /** ptr to the next byte in the current fragment */
192 /** count of bytes remaining in the current descriptor */
196 /** rx State Machine */
200 /** Current Receive Descriptor Done */
202 /** num of bytes in the current packet being drained from rxDataFifo */
204 /** halt the rx state machine after current packet */
206 /** ptr to the next byte in current fragment */
208 /** count of bytes remaining in the current descriptor */
226 void rxDmaReadCopy();
227 void rxDmaWriteCopy();
234 void txDmaReadCopy();
235 void txDmaWriteCopy();
237 void rxDmaReadDone();
238 friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
239 EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
241 void rxDmaWriteDone();
242 friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
243 EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
245 void txDmaReadDone();
246 friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
247 EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
249 void txDmaWriteDone();
250 friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
251 EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
267 typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
268 friend void RxKickEvent::process();
272 typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
273 friend void TxKickEvent::process();
279 void txEventTransmit()
282 if (txState == txFifoBlock)
285 typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
286 friend void TxEvent::process();
293 * receive address filter
296 bool rxFilter(const PacketPtr &packet);
297 bool acceptBroadcast;
298 bool acceptMulticast;
303 PhysicalMemory *physmem;
306 * Interrupt management
308 void devIntrPost(uint32_t interrupts);
309 void devIntrClear(uint32_t interrupts);
310 void devIntrChangeMask();
315 void cpuIntrPost(Tick when);
319 typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
320 friend void IntrEvent::process();
321 IntrEvent *intrEvent;
322 NSGigEInt *interface;
325 struct Params : public PciDev::Params
327 PhysicalMemory *pmem;
339 Tick dma_write_delay;
340 Tick dma_read_factor;
341 Tick dma_write_factor;
344 uint32_t tx_fifo_size;
345 uint32_t rx_fifo_size;
347 bool dma_no_allocate;
350 NSGigE(Params *params);
352 const Params *params() const { return (const Params *)_params; }
354 virtual void WriteConfig(int offset, int size, uint32_t data);
355 virtual void ReadConfig(int offset, int size, uint8_t *data);
357 virtual Fault read(MemReqPtr &req, uint8_t *data);
358 virtual Fault write(MemReqPtr &req, const uint8_t *data);
360 bool cpuIntrPending() const;
361 void cpuIntrAck() { cpuIntrClear(); }
363 bool recvPacket(PacketPtr packet);
366 void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
368 virtual void serialize(std::ostream &os);
369 virtual void unserialize(Checkpoint *cp, const std::string §ion);
375 Stats::Scalar<> txBytes;
376 Stats::Scalar<> rxBytes;
377 Stats::Scalar<> txPackets;
378 Stats::Scalar<> rxPackets;
379 Stats::Scalar<> txIpChecksums;
380 Stats::Scalar<> rxIpChecksums;
381 Stats::Scalar<> txTcpChecksums;
382 Stats::Scalar<> rxTcpChecksums;
383 Stats::Scalar<> txUdpChecksums;
384 Stats::Scalar<> rxUdpChecksums;
385 Stats::Scalar<> descDmaReads;
386 Stats::Scalar<> descDmaWrites;
387 Stats::Scalar<> descDmaRdBytes;
388 Stats::Scalar<> descDmaWrBytes;
389 Stats::Formula totBandwidth;
390 Stats::Formula totPackets;
391 Stats::Formula totBytes;
392 Stats::Formula totPacketRate;
393 Stats::Formula txBandwidth;
394 Stats::Formula rxBandwidth;
395 Stats::Formula txPacketRate;
396 Stats::Formula rxPacketRate;
397 Stats::Scalar<> postedSwi;
398 Stats::Formula coalescedSwi;
399 Stats::Scalar<> totalSwi;
400 Stats::Scalar<> postedRxIdle;
401 Stats::Formula coalescedRxIdle;
402 Stats::Scalar<> totalRxIdle;
403 Stats::Scalar<> postedRxOk;
404 Stats::Formula coalescedRxOk;
405 Stats::Scalar<> totalRxOk;
406 Stats::Scalar<> postedRxDesc;
407 Stats::Formula coalescedRxDesc;
408 Stats::Scalar<> totalRxDesc;
409 Stats::Scalar<> postedTxOk;
410 Stats::Formula coalescedTxOk;
411 Stats::Scalar<> totalTxOk;
412 Stats::Scalar<> postedTxIdle;
413 Stats::Formula coalescedTxIdle;
414 Stats::Scalar<> totalTxIdle;
415 Stats::Scalar<> postedTxDesc;
416 Stats::Formula coalescedTxDesc;
417 Stats::Scalar<> totalTxDesc;
418 Stats::Scalar<> postedRxOrn;
419 Stats::Formula coalescedRxOrn;
420 Stats::Scalar<> totalRxOrn;
421 Stats::Formula coalescedTotal;
422 Stats::Scalar<> postedInterrupts;
423 Stats::Scalar<> droppedPackets;
426 Tick cacheAccess(MemReqPtr &req);
430 * Ethernet Interface for an Ethernet Device
432 class NSGigEInt : public EtherInt
438 NSGigEInt(const std::string &name, NSGigE *d)
439 : EtherInt(name), dev(d) { dev->setInterface(this); }
441 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
442 virtual void sendDone() { dev->transferDone(); }
445 #endif // __DEV_NS_GIGE_HH__