dev/ns_gige.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Device module for modelling the National Semiconductor
  31  * DP83820 ethernet controller
  32  */
  33
  34 #ifndef __DEV_NS_GIGE_HH__
  35 #define __DEV_NS_GIGE_HH__
  36
  37 #include "base/inet.hh"
  38 #include "base/statistics.hh"
  39 #include "dev/etherint.hh"
  40 #include "dev/etherpkt.hh"
  41 #include "dev/io_device.hh"
  42 #include "dev/ns_gige_reg.h"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pktfifo.hh"
  45 #include "mem/bus/bus.hh"
  46 #include "sim/eventq.hh"
  47
  48 // Hash filtering constants
  49 const uint16_t FHASH_ADDR  = 0x100;
  50 const uint16_t FHASH_SIZE  = 0x100;
  51
  52 // EEPROM constants
  53 const uint8_t  EEPROM_READ = 0x2;
  54 const uint8_t  EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
  55 const uint8_t  EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
  56 const uint8_t  EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
  57 const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
  58
  59 /**
  60  * Ethernet device registers
  61  */
  62 struct dp_regs {
  63     uint32_t    command;
  64     uint32_t    config;
  65     uint32_t    mear;
  66     uint32_t    ptscr;
  67     uint32_t    isr;
  68     uint32_t    imr;
  69     uint32_t    ier;
  70     uint32_t    ihr;
  71     uint32_t    txdp;
  72     uint32_t    txdp_hi;
  73     uint32_t    txcfg;
  74     uint32_t    gpior;
  75     uint32_t    rxdp;
  76     uint32_t    rxdp_hi;
  77     uint32_t    rxcfg;
  78     uint32_t    pqcr;
  79     uint32_t    wcsr;
  80     uint32_t    pcr;
  81     uint32_t    rfcr;
  82     uint32_t    rfdr;
  83     uint32_t    brar;
  84     uint32_t    brdr;
  85     uint32_t    srr;
  86     uint32_t    mibc;
  87     uint32_t    vrcr;
  88     uint32_t    vtcr;
  89     uint32_t    vdr;
  90     uint32_t    ccsr;
  91     uint32_t    tbicr;
  92     uint32_t    tbisr;
  93     uint32_t    tanar;
  94     uint32_t    tanlpar;
  95     uint32_t    taner;
  96     uint32_t    tesr;
  97 };
  98
  99 struct dp_rom {
 100     /**
 101      * for perfect match memory.
 102      * the linux driver doesn't use any other ROM
 103      */
 104     uint8_t perfectMatch[ETH_ADDR_LEN];
 105
 106     /**
 107      * for hash table memory.
 108      * used by the freebsd driver
 109      */
 110     uint8_t filterHash[FHASH_SIZE];
 111 };
 112
 113 class NSGigEInt;
 114 class PhysicalMemory;
 115 class BaseInterface;
 116 class HierParams;
 117 class Bus;
 118 class PciConfigAll;
 119
 120 /**
 121  * NS DP83820 Ethernet device model
 122  */
 123 class NSGigE : public PciDev
 124 {
 125   public:
 126     /** Transmit State Machine states */
 127     enum TxState
 128     {
 129         txIdle,
 130         txDescRefr,
 131         txDescRead,
 132         txFifoBlock,
 133         txFragRead,
 134         txDescWrite,
 135         txAdvance
 136     };
 137
 138     /** Receive State Machine States */
 139     enum RxState
 140     {
 141         rxIdle,
 142         rxDescRefr,
 143         rxDescRead,
 144         rxFifoBlock,
 145         rxFragWrite,
 146         rxDescWrite,
 147         rxAdvance
 148     };
 149
 150     enum DmaState
 151     {
 152         dmaIdle,
 153         dmaReading,
 154         dmaWriting,
 155         dmaReadWaiting,
 156         dmaWriteWaiting
 157     };
 158
 159     /** EEPROM State Machine States */
 160     enum EEPROMState
 161     {
 162         eepromStart,
 163         eepromGetOpcode,
 164         eepromGetAddress,
 165         eepromRead
 166     };
 167
 168   private:
 169     Addr addr;
 170     static const Addr size = sizeof(dp_regs);
 171
 172   protected:
 173     /** device register file */
 174     dp_regs regs;
 175     dp_rom rom;
 176
 177     /** pci settings */
 178     bool ioEnable;
 179 #if 0
 180     bool memEnable;
 181     bool bmEnable;
 182 #endif
 183
 184     /*** BASIC STRUCTURES FOR TX/RX ***/
 185     /* Data FIFOs */
 186     PacketFifo txFifo;
 187     PacketFifo rxFifo;
 188
 189     /** various helper vars */
 190     PacketPtr txPacket;
 191     PacketPtr rxPacket;
 192     uint8_t *txPacketBufPtr;
 193     uint8_t *rxPacketBufPtr;
 194     uint32_t txXferLen;
 195     uint32_t rxXferLen;
 196     bool rxDmaFree;
 197     bool txDmaFree;
 198
 199     /** DescCaches */
 200     ns_desc32 txDesc32;
 201     ns_desc32 rxDesc32;
 202     ns_desc64 txDesc64;
 203     ns_desc64 rxDesc64;
 204
 205     /* state machine cycle time */
 206     Tick clock;
 207     inline Tick cycles(int numCycles) const { return numCycles * clock; }
 208
 209     /* tx State Machine */
 210     TxState txState;
 211     bool txEnable;
 212
 213     /** Current Transmit Descriptor Done */
 214     bool CTDD;
 215     /** halt the tx state machine after next packet */
 216     bool txHalt;
 217     /** ptr to the next byte in the current fragment */
 218     Addr txFragPtr;
 219     /** count of bytes remaining in the current descriptor */
 220     uint32_t txDescCnt;
 221     DmaState txDmaState;
 222
 223     /** rx State Machine */
 224     RxState rxState;
 225     bool rxEnable;
 226
 227     /** Current Receive Descriptor Done */
 228     bool CRDD;
 229     /** num of bytes in the current packet being drained from rxDataFifo */
 230     uint32_t rxPktBytes;
 231     /** halt the rx state machine after current packet */
 232     bool rxHalt;
 233     /** ptr to the next byte in current fragment */
 234     Addr rxFragPtr;
 235     /** count of bytes remaining in the current descriptor */
 236     uint32_t rxDescCnt;
 237     DmaState rxDmaState;
 238
 239     struct RegWriteData {
 240         Addr daddr;
 241         uint32_t value;
 242         RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
 243     };
 244
 245     std::vector<std::list<RegWriteData> > writeQueue;
 246     bool pioDelayWrite;
 247
 248     bool extstsEnable;
 249
 250     /** EEPROM State Machine */
 251     EEPROMState eepromState;
 252     bool eepromClk;
 253     uint8_t eepromBitsToRx;
 254     uint8_t eepromOpcode;
 255     uint8_t eepromAddress;
 256     uint16_t eepromData;
 257
 258   protected:
 259     Tick dmaReadDelay;
 260     Tick dmaWriteDelay;
 261
 262     Tick dmaReadFactor;
 263     Tick dmaWriteFactor;
 264
 265     void *rxDmaData;
 266     Addr  rxDmaAddr;
 267     int   rxDmaLen;
 268     bool  doRxDmaRead();
 269     bool  doRxDmaWrite();
 270     void  rxDmaReadCopy();
 271     void  rxDmaWriteCopy();
 272
 273     void *txDmaData;
 274     Addr  txDmaAddr;
 275     int   txDmaLen;
 276     bool  doTxDmaRead();
 277     bool  doTxDmaWrite();
 278     void  txDmaReadCopy();
 279     void  txDmaWriteCopy();
 280
 281     void rxDmaReadDone();
 282     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
 283     EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 284
 285     void rxDmaWriteDone();
 286     friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
 287     EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 288
 289     void txDmaReadDone();
 290     friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
 291     EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 292
 293     void txDmaWriteDone();
 294     friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
 295     EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 296
 297     bool dmaDescFree;
 298     bool dmaDataFree;
 299
 300   protected:
 301     Tick txDelay;
 302     Tick rxDelay;
 303
 304     void txReset();
 305     void rxReset();
 306     void regsReset();
 307
 308     void rxKick();
 309     Tick rxKickTick;
 310     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
 311     friend void RxKickEvent::process();
 312     RxKickEvent rxKickEvent;
 313
 314     void txKick();
 315     Tick txKickTick;
 316     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
 317     friend void TxKickEvent::process();
 318     TxKickEvent txKickEvent;
 319
 320     void eepromKick();
 321
 322     /**
 323      * Retransmit event
 324      */
 325     void transmit();
 326     void txEventTransmit()
 327     {
 328         transmit();
 329         if (txState == txFifoBlock)
 330             txKick();
 331     }
 332     typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
 333     friend void TxEvent::process();
 334     TxEvent txEvent;
 335
 336     void txDump() const;
 337     void rxDump() const;
 338
 339     /**
 340      * receive address filter
 341      */
 342     bool rxFilterEnable;
 343     bool rxFilter(const PacketPtr &packet);
 344     bool acceptBroadcast;
 345     bool acceptMulticast;
 346     bool acceptUnicast;
 347     bool acceptPerfect;
 348     bool acceptArp;
 349     bool multicastHashEnable;
 350
 351     PhysicalMemory *physmem;
 352
 353     /**
 354      * Interrupt management
 355      */
 356     void devIntrPost(uint32_t interrupts);
 357     void devIntrClear(uint32_t interrupts);
 358     void devIntrChangeMask();
 359
 360     Tick intrDelay;
 361     Tick intrTick;
 362     bool cpuPendingIntr;
 363     void cpuIntrPost(Tick when);
 364     void cpuInterrupt();
 365     void cpuIntrClear();
 366
 367     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
 368     friend void IntrEvent::process();
 369     IntrEvent *intrEvent;
 370     NSGigEInt *interface;
 371
 372   public:
 373     struct Params : public PciDev::Params
 374     {
 375         PhysicalMemory *pmem;
 376         HierParams *hier;
 377         Bus *pio_bus;
 378         Bus *header_bus;
 379         Bus *payload_bus;
 380         Tick clock;
 381         Tick intr_delay;
 382         Tick tx_delay;
 383         Tick rx_delay;
 384         Tick pio_latency;
 385         bool pio_delay_write;
 386         bool dma_desc_free;
 387         bool dma_data_free;
 388         Tick dma_read_delay;
 389         Tick dma_write_delay;
 390         Tick dma_read_factor;
 391         Tick dma_write_factor;
 392         bool rx_filter;
 393         Net::EthAddr eaddr;
 394         uint32_t tx_fifo_size;
 395         uint32_t rx_fifo_size;
 396         bool rx_thread;
 397         bool tx_thread;
 398         bool dma_no_allocate;
 399     };
 400
 401     NSGigE(Params *params);
 402     ~NSGigE();
 403     const Params *params() const { return (const Params *)_params; }
 404
 405     virtual void writeConfig(int offset, int size, const uint8_t *data);
 406     virtual void readConfig(int offset, int size, uint8_t *data);
 407
 408     virtual Fault * read(MemReqPtr &req, uint8_t *data);
 409     virtual Fault * write(MemReqPtr &req, const uint8_t *data);
 410
 411     bool cpuIntrPending() const;
 412     void cpuIntrAck() { cpuIntrClear(); }
 413
 414     bool recvPacket(PacketPtr packet);
 415     void transferDone();
 416
 417     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 418
 419     virtual void serialize(std::ostream &os);
 420     virtual void unserialize(Checkpoint *cp, const std::string &section);
 421
 422   public:
 423     void regStats();
 424
 425   private:
 426     Stats::Scalar<> txBytes;
 427     Stats::Scalar<> rxBytes;
 428     Stats::Scalar<> txPackets;
 429     Stats::Scalar<> rxPackets;
 430     Stats::Scalar<> txIpChecksums;
 431     Stats::Scalar<> rxIpChecksums;
 432     Stats::Scalar<> txTcpChecksums;
 433     Stats::Scalar<> rxTcpChecksums;
 434     Stats::Scalar<> txUdpChecksums;
 435     Stats::Scalar<> rxUdpChecksums;
 436     Stats::Scalar<> descDmaReads;
 437     Stats::Scalar<> descDmaWrites;
 438     Stats::Scalar<> descDmaRdBytes;
 439     Stats::Scalar<> descDmaWrBytes;
 440     Stats::Formula totBandwidth;
 441     Stats::Formula totPackets;
 442     Stats::Formula totBytes;
 443     Stats::Formula totPacketRate;
 444     Stats::Formula txBandwidth;
 445     Stats::Formula rxBandwidth;
 446     Stats::Formula txPacketRate;
 447     Stats::Formula rxPacketRate;
 448     Stats::Scalar<> postedSwi;
 449     Stats::Formula coalescedSwi;
 450     Stats::Scalar<> totalSwi;
 451     Stats::Scalar<> postedRxIdle;
 452     Stats::Formula coalescedRxIdle;
 453     Stats::Scalar<> totalRxIdle;
 454     Stats::Scalar<> postedRxOk;
 455     Stats::Formula coalescedRxOk;
 456     Stats::Scalar<> totalRxOk;
 457     Stats::Scalar<> postedRxDesc;
 458     Stats::Formula coalescedRxDesc;
 459     Stats::Scalar<> totalRxDesc;
 460     Stats::Scalar<> postedTxOk;
 461     Stats::Formula coalescedTxOk;
 462     Stats::Scalar<> totalTxOk;
 463     Stats::Scalar<> postedTxIdle;
 464     Stats::Formula coalescedTxIdle;
 465     Stats::Scalar<> totalTxIdle;
 466     Stats::Scalar<> postedTxDesc;
 467     Stats::Formula coalescedTxDesc;
 468     Stats::Scalar<> totalTxDesc;
 469     Stats::Scalar<> postedRxOrn;
 470     Stats::Formula coalescedRxOrn;
 471     Stats::Scalar<> totalRxOrn;
 472     Stats::Formula coalescedTotal;
 473     Stats::Scalar<> postedInterrupts;
 474     Stats::Scalar<> droppedPackets;
 475
 476   public:
 477     Tick cacheAccess(MemReqPtr &req);
 478 };
 479
 480 /*
 481  * Ethernet Interface for an Ethernet Device
 482  */
 483 class NSGigEInt : public EtherInt
 484 {
 485   private:
 486     NSGigE *dev;
 487
 488   public:
 489     NSGigEInt(const std::string &name, NSGigE *d)
 490         : EtherInt(name), dev(d) { dev->setInterface(this); }
 491
 492     virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
 493     virtual void sendDone() { dev->transferDone(); }
 494 };
 495
 496 #endif // __DEV_NS_GIGE_HH__