dev/ns_gige.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @file
  30  * Device module for modelling the National Semiconductor
  31  * DP83820 ethernet controller
  32  */
  33
  34 #ifndef __DEV_NS_GIGE_HH__
  35 #define __DEV_NS_GIGE_HH__
  36
  37 #include "base/inet.hh"
  38 #include "base/statistics.hh"
  39 #include "dev/etherint.hh"
  40 #include "dev/etherpkt.hh"
  41 #include "dev/io_device.hh"
  42 #include "dev/ns_gige_reg.h"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pktfifo.hh"
  45 #include "mem/bus/bus.hh"
  46 #include "sim/eventq.hh"
  47
  48 // Hash filtering constants
  49 const uint16_t FHASH_ADDR  = 0x100;
  50 const uint16_t FHASH_SIZE  = 0x100;
  51
  52 // EEPROM constants
  53 const uint8_t  EEPROM_READ = 0x2;
  54 const uint8_t  EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM
  55 const uint8_t  EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2
  56 const uint8_t  EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1
  57 const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
  58
  59 /**
  60  * Ethernet device registers
  61  */
  62 struct dp_regs {
  63     uint32_t    command;
  64     uint32_t    config;
  65     uint32_t    mear;
  66     uint32_t    ptscr;
  67     uint32_t    isr;
  68     uint32_t    imr;
  69     uint32_t    ier;
  70     uint32_t    ihr;
  71     uint32_t    txdp;
  72     uint32_t    txdp_hi;
  73     uint32_t    txcfg;
  74     uint32_t    gpior;
  75     uint32_t    rxdp;
  76     uint32_t    rxdp_hi;
  77     uint32_t    rxcfg;
  78     uint32_t    pqcr;
  79     uint32_t    wcsr;
  80     uint32_t    pcr;
  81     uint32_t    rfcr;
  82     uint32_t    rfdr;
  83     uint32_t    brar;
  84     uint32_t    brdr;
  85     uint32_t    srr;
  86     uint32_t    mibc;
  87     uint32_t    vrcr;
  88     uint32_t    vtcr;
  89     uint32_t    vdr;
  90     uint32_t    ccsr;
  91     uint32_t    tbicr;
  92     uint32_t    tbisr;
  93     uint32_t    tanar;
  94     uint32_t    tanlpar;
  95     uint32_t    taner;
  96     uint32_t    tesr;
  97 };
  98
  99 struct dp_rom {
 100     /**
 101      * for perfect match memory.
 102      * the linux driver doesn't use any other ROM
 103      */
 104     uint8_t perfectMatch[ETH_ADDR_LEN];
 105
 106     /**
 107      * for hash table memory.
 108      * used by the freebsd driver
 109      */
 110     uint8_t filterHash[FHASH_SIZE];
 111 };
 112
 113 class NSGigEInt;
 114 class PhysicalMemory;
 115 class BaseInterface;
 116 class HierParams;
 117 class Bus;
 118 class PciConfigAll;
 119
 120 /**
 121  * NS DP83820 Ethernet device model
 122  */
 123 class NSGigE : public PciDev
 124 {
 125   public:
 126     /** Transmit State Machine states */
 127     enum TxState
 128     {
 129         txIdle,
 130         txDescRefr,
 131         txDescRead,
 132         txFifoBlock,
 133         txFragRead,
 134         txDescWrite,
 135         txAdvance
 136     };
 137
 138     /** Receive State Machine States */
 139     enum RxState
 140     {
 141         rxIdle,
 142         rxDescRefr,
 143         rxDescRead,
 144         rxFifoBlock,
 145         rxFragWrite,
 146         rxDescWrite,
 147         rxAdvance
 148     };
 149
 150     enum DmaState
 151     {
 152         dmaIdle,
 153         dmaReading,
 154         dmaWriting,
 155         dmaReadWaiting,
 156         dmaWriteWaiting
 157     };
 158
 159     /** EEPROM State Machine States */
 160     enum EEPROMState
 161     {
 162         eepromStart,
 163         eepromGetOpcode,
 164         eepromGetAddress,
 165         eepromRead
 166     };
 167
 168   private:
 169     Addr addr;
 170     static const Addr size = sizeof(dp_regs);
 171
 172   protected:
 173     typedef std::deque<PacketPtr> pktbuf_t;
 174     typedef pktbuf_t::iterator pktiter_t;
 175
 176     /** device register file */
 177     dp_regs regs;
 178     dp_rom rom;
 179
 180     /** pci settings */
 181     bool ioEnable;
 182 #if 0
 183     bool memEnable;
 184     bool bmEnable;
 185 #endif
 186
 187     /*** BASIC STRUCTURES FOR TX/RX ***/
 188     /* Data FIFOs */
 189     PacketFifo txFifo;
 190     PacketFifo rxFifo;
 191
 192     /** various helper vars */
 193     PacketPtr txPacket;
 194     PacketPtr rxPacket;
 195     uint8_t *txPacketBufPtr;
 196     uint8_t *rxPacketBufPtr;
 197     uint32_t txXferLen;
 198     uint32_t rxXferLen;
 199     bool rxDmaFree;
 200     bool txDmaFree;
 201
 202     /** DescCaches */
 203     ns_desc32 txDesc32;
 204     ns_desc32 rxDesc32;
 205     ns_desc64 txDesc64;
 206     ns_desc64 rxDesc64;
 207
 208     /* state machine cycle time */
 209     Tick clock;
 210     inline Tick cycles(int numCycles) const { return numCycles * clock; }
 211
 212     /* tx State Machine */
 213     TxState txState;
 214     bool txEnable;
 215
 216     /** Current Transmit Descriptor Done */
 217     bool CTDD;
 218     /** halt the tx state machine after next packet */
 219     bool txHalt;
 220     /** ptr to the next byte in the current fragment */
 221     Addr txFragPtr;
 222     /** count of bytes remaining in the current descriptor */
 223     uint32_t txDescCnt;
 224     DmaState txDmaState;
 225
 226     /** rx State Machine */
 227     RxState rxState;
 228     bool rxEnable;
 229
 230     /** Current Receive Descriptor Done */
 231     bool CRDD;
 232     /** num of bytes in the current packet being drained from rxDataFifo */
 233     uint32_t rxPktBytes;
 234     /** halt the rx state machine after current packet */
 235     bool rxHalt;
 236     /** ptr to the next byte in current fragment */
 237     Addr rxFragPtr;
 238     /** count of bytes remaining in the current descriptor */
 239     uint32_t rxDescCnt;
 240     DmaState rxDmaState;
 241
 242     struct RegWriteData {
 243         Addr daddr;
 244         uint32_t value;
 245         RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
 246     };
 247
 248     std::vector<std::list<RegWriteData> > writeQueue;
 249     bool pioDelayWrite;
 250
 251     bool extstsEnable;
 252
 253     /** EEPROM State Machine */
 254     EEPROMState eepromState;
 255     bool eepromClk;
 256     uint8_t eepromBitsToRx;
 257     uint8_t eepromOpcode;
 258     uint8_t eepromAddress;
 259     uint16_t eepromData;
 260
 261   protected:
 262     Tick dmaReadDelay;
 263     Tick dmaWriteDelay;
 264
 265     Tick dmaReadFactor;
 266     Tick dmaWriteFactor;
 267
 268     void *rxDmaData;
 269     Addr  rxDmaAddr;
 270     int   rxDmaLen;
 271     bool  doRxDmaRead();
 272     bool  doRxDmaWrite();
 273     void  rxDmaReadCopy();
 274     void  rxDmaWriteCopy();
 275
 276     void *txDmaData;
 277     Addr  txDmaAddr;
 278     int   txDmaLen;
 279     bool  doTxDmaRead();
 280     bool  doTxDmaWrite();
 281     void  txDmaReadCopy();
 282     void  txDmaWriteCopy();
 283
 284     void rxDmaReadDone();
 285     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
 286     EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
 287
 288     void rxDmaWriteDone();
 289     friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
 290     EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
 291
 292     void txDmaReadDone();
 293     friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
 294     EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
 295
 296     void txDmaWriteDone();
 297     friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
 298     EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
 299
 300     bool dmaDescFree;
 301     bool dmaDataFree;
 302
 303   protected:
 304     Tick txDelay;
 305     Tick rxDelay;
 306
 307     void txReset();
 308     void rxReset();
 309     void regsReset();
 310
 311     void rxKick();
 312     Tick rxKickTick;
 313     typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
 314     friend void RxKickEvent::process();
 315     RxKickEvent rxKickEvent;
 316
 317     void txKick();
 318     Tick txKickTick;
 319     typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
 320     friend void TxKickEvent::process();
 321     TxKickEvent txKickEvent;
 322
 323     void eepromKick();
 324
 325     /**
 326      * Retransmit event
 327      */
 328     void transmit();
 329     void txEventTransmit()
 330     {
 331         transmit();
 332         if (txState == txFifoBlock)
 333             txKick();
 334     }
 335     typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
 336     friend void TxEvent::process();
 337     TxEvent txEvent;
 338
 339     void txDump() const;
 340     void rxDump() const;
 341
 342     /**
 343      * receive address filter
 344      */
 345     bool rxFilterEnable;
 346     bool rxFilter(const PacketPtr &packet);
 347     bool acceptBroadcast;
 348     bool acceptMulticast;
 349     bool acceptUnicast;
 350     bool acceptPerfect;
 351     bool acceptArp;
 352     bool multicastHashEnable;
 353
 354     PhysicalMemory *physmem;
 355
 356     /**
 357      * Interrupt management
 358      */
 359     void devIntrPost(uint32_t interrupts);
 360     void devIntrClear(uint32_t interrupts);
 361     void devIntrChangeMask();
 362
 363     Tick intrDelay;
 364     Tick intrTick;
 365     bool cpuPendingIntr;
 366     void cpuIntrPost(Tick when);
 367     void cpuInterrupt();
 368     void cpuIntrClear();
 369
 370     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
 371     friend void IntrEvent::process();
 372     IntrEvent *intrEvent;
 373     NSGigEInt *interface;
 374
 375   public:
 376     struct Params : public PciDev::Params
 377     {
 378         PhysicalMemory *pmem;
 379         HierParams *hier;
 380         Bus *pio_bus;
 381         Bus *header_bus;
 382         Bus *payload_bus;
 383         Tick clock;
 384         Tick intr_delay;
 385         Tick tx_delay;
 386         Tick rx_delay;
 387         Tick pio_latency;
 388         bool pio_delay_write;
 389         bool dma_desc_free;
 390         bool dma_data_free;
 391         Tick dma_read_delay;
 392         Tick dma_write_delay;
 393         Tick dma_read_factor;
 394         Tick dma_write_factor;
 395         bool rx_filter;
 396         Net::EthAddr eaddr;
 397         uint32_t tx_fifo_size;
 398         uint32_t rx_fifo_size;
 399         bool dedicated;
 400         bool dma_no_allocate;
 401     };
 402
 403     NSGigE(Params *params);
 404     ~NSGigE();
 405     const Params *params() const { return (const Params *)_params; }
 406
 407     virtual void writeConfig(int offset, int size, const uint8_t *data);
 408     virtual void readConfig(int offset, int size, uint8_t *data);
 409
 410     virtual Fault read(MemReqPtr &req, uint8_t *data);
 411     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 412
 413     bool cpuIntrPending() const;
 414     void cpuIntrAck() { cpuIntrClear(); }
 415
 416     bool recvPacket(PacketPtr packet);
 417     void transferDone();
 418
 419     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
 420
 421     virtual void serialize(std::ostream &os);
 422     virtual void unserialize(Checkpoint *cp, const std::string &section);
 423
 424   public:
 425     void regStats();
 426
 427   private:
 428     Stats::Scalar<> txBytes;
 429     Stats::Scalar<> rxBytes;
 430     Stats::Scalar<> txPackets;
 431     Stats::Scalar<> rxPackets;
 432     Stats::Scalar<> txIpChecksums;
 433     Stats::Scalar<> rxIpChecksums;
 434     Stats::Scalar<> txTcpChecksums;
 435     Stats::Scalar<> rxTcpChecksums;
 436     Stats::Scalar<> txUdpChecksums;
 437     Stats::Scalar<> rxUdpChecksums;
 438     Stats::Scalar<> descDmaReads;
 439     Stats::Scalar<> descDmaWrites;
 440     Stats::Scalar<> descDmaRdBytes;
 441     Stats::Scalar<> descDmaWrBytes;
 442     Stats::Formula totBandwidth;
 443     Stats::Formula totPackets;
 444     Stats::Formula totBytes;
 445     Stats::Formula totPacketRate;
 446     Stats::Formula txBandwidth;
 447     Stats::Formula rxBandwidth;
 448     Stats::Formula txPacketRate;
 449     Stats::Formula rxPacketRate;
 450     Stats::Scalar<> postedSwi;
 451     Stats::Formula coalescedSwi;
 452     Stats::Scalar<> totalSwi;
 453     Stats::Scalar<> postedRxIdle;
 454     Stats::Formula coalescedRxIdle;
 455     Stats::Scalar<> totalRxIdle;
 456     Stats::Scalar<> postedRxOk;
 457     Stats::Formula coalescedRxOk;
 458     Stats::Scalar<> totalRxOk;
 459     Stats::Scalar<> postedRxDesc;
 460     Stats::Formula coalescedRxDesc;
 461     Stats::Scalar<> totalRxDesc;
 462     Stats::Scalar<> postedTxOk;
 463     Stats::Formula coalescedTxOk;
 464     Stats::Scalar<> totalTxOk;
 465     Stats::Scalar<> postedTxIdle;
 466     Stats::Formula coalescedTxIdle;
 467     Stats::Scalar<> totalTxIdle;
 468     Stats::Scalar<> postedTxDesc;
 469     Stats::Formula coalescedTxDesc;
 470     Stats::Scalar<> totalTxDesc;
 471     Stats::Scalar<> postedRxOrn;
 472     Stats::Formula coalescedRxOrn;
 473     Stats::Scalar<> totalRxOrn;
 474     Stats::Formula coalescedTotal;
 475     Stats::Scalar<> postedInterrupts;
 476     Stats::Scalar<> droppedPackets;
 477
 478   public:
 479     Tick cacheAccess(MemReqPtr &req);
 480 };
 481
 482 /*
 483  * Ethernet Interface for an Ethernet Device
 484  */
 485 class NSGigEInt : public EtherInt
 486 {
 487   private:
 488     NSGigE *dev;
 489
 490   public:
 491     NSGigEInt(const std::string &name, NSGigE *d)
 492         : EtherInt(name), dev(d) { dev->setInterface(this); }
 493
 494     virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
 495     virtual void sendDone() { dev->transferDone(); }
 496 };
 497
 498 #endif // __DEV_NS_GIGE_HH__