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30 * Ethernet device register definitions for the National
31 * Semiconductor DP83820 Ethernet controller
34 #ifndef __DEV_NS_GIGE_REG_H__
35 #define __DEV_NS_GIGE_REG_H__
37 /* Device Register Address Map */
62 #define MIB_START 0x60
78 /* Chip Command Register */
79 #define CR_TXE 0x00000001
80 #define CR_TXD 0x00000002
81 #define CR_RXE 0x00000004
82 #define CR_RXD 0x00000008
83 #define CR_TXR 0x00000010
84 #define CR_RXR 0x00000020
85 #define CR_SWI 0x00000080
86 #define CR_RST 0x00000100
88 /* configuration register */
89 #define CFGR_LNKSTS 0x80000000
90 #define CFGR_SPDSTS 0x60000000
91 #define CFGR_SPDSTS1 0x40000000
92 #define CFGR_SPDSTS0 0x20000000
93 #define CFGR_DUPSTS 0x10000000
94 #define CFGR_TBI_EN 0x01000000
95 #define CFGR_RESERVED 0x0e000000
96 #define CFGR_MODE_1000 0x00400000
97 #define CFGR_AUTO_1000 0x00200000
98 #define CFGR_PINT_CTL 0x001c0000
99 #define CFGR_PINT_DUPSTS 0x00100000
100 #define CFGR_PINT_LNKSTS 0x00080000
101 #define CFGR_PINT_SPDSTS 0x00040000
102 #define CFGR_TMRTEST 0x00020000
103 #define CFGR_MRM_DIS 0x00010000
104 #define CFGR_MWI_DIS 0x00008000
105 #define CFGR_T64ADDR 0x00004000
106 #define CFGR_PCI64_DET 0x00002000
107 #define CFGR_DATA64_EN 0x00001000
108 #define CFGR_M64ADDR 0x00000800
109 #define CFGR_PHY_RST 0x00000400
110 #define CFGR_PHY_DIS 0x00000200
111 #define CFGR_EXTSTS_EN 0x00000100
112 #define CFGR_REQALG 0x00000080
113 #define CFGR_SB 0x00000040
114 #define CFGR_POW 0x00000020
115 #define CFGR_EXD 0x00000010
116 #define CFGR_PESEL 0x00000008
117 #define CFGR_BROM_DIS 0x00000004
118 #define CFGR_EXT_125 0x00000002
119 #define CFGR_BEM 0x00000001
121 /* EEPROM access register */
122 #define MEAR_EEDI 0x00000001
123 #define MEAR_EEDO 0x00000002
124 #define MEAR_EECLK 0x00000004
125 #define MEAR_EESEL 0x00000008
126 #define MEAR_MDIO 0x00000010
127 #define MEAR_MDDIR 0x00000020
128 #define MEAR_MDC 0x00000040
130 /* PCI test control register */
131 #define PTSCR_EEBIST_FAIL 0x00000001
132 #define PTSCR_EEBIST_EN 0x00000002
133 #define PTSCR_EELOAD_EN 0x00000004
134 #define PTSCR_RBIST_FAIL 0x000001b8
135 #define PTSCR_RBIST_DONE 0x00000200
136 #define PTSCR_RBIST_EN 0x00000400
137 #define PTSCR_RBIST_RST 0x00002000
138 #define PTSCR_RBIST_RDONLY 0x000003f9
140 /* interrupt status register */
141 #define ISR_RESERVE 0x80000000
142 #define ISR_TXDESC3 0x40000000
143 #define ISR_TXDESC2 0x20000000
144 #define ISR_TXDESC1 0x10000000
145 #define ISR_TXDESC0 0x08000000
146 #define ISR_RXDESC3 0x04000000
147 #define ISR_RXDESC2 0x02000000
148 #define ISR_RXDESC1 0x01000000
149 #define ISR_RXDESC0 0x00800000
150 #define ISR_TXRCMP 0x00400000
151 #define ISR_RXRCMP 0x00200000
152 #define ISR_DPERR 0x00100000
153 #define ISR_SSERR 0x00080000
154 #define ISR_RMABT 0x00040000
155 #define ISR_RTABT 0x00020000
156 #define ISR_RXSOVR 0x00010000
157 #define ISR_HIBINT 0x00008000
158 #define ISR_PHY 0x00004000
159 #define ISR_PME 0x00002000
160 #define ISR_SWI 0x00001000
161 #define ISR_MIB 0x00000800
162 #define ISR_TXURN 0x00000400
163 #define ISR_TXIDLE 0x00000200
164 #define ISR_TXERR 0x00000100
165 #define ISR_TXDESC 0x00000080
166 #define ISR_TXOK 0x00000040
167 #define ISR_RXORN 0x00000020
168 #define ISR_RXIDLE 0x00000010
169 #define ISR_RXEARLY 0x00000008
170 #define ISR_RXERR 0x00000004
171 #define ISR_RXDESC 0x00000002
172 #define ISR_RXOK 0x00000001
173 #define ISR_ALL 0x7FFFFFFF
174 #define ISR_DELAY (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \
175 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
176 #define ISR_NODELAY (ISR_ALL & ~ISR_DELAY)
177 #define ISR_IMPL (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
178 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
179 #define ISR_NOIMPL (ISR_ALL & ~ISR_IMPL)
181 /* transmit configuration register */
182 #define TX_CFG_CSI 0x80000000
183 #define TX_CFG_HBI 0x40000000
184 #define TX_CFG_MLB 0x20000000
185 #define TX_CFG_ATP 0x10000000
186 #define TX_CFG_ECRETRY 0x00800000
187 #define TX_CFG_BRST_DIS 0x00080000
188 #define TX_CFG_MXDMA1024 0x00000000
189 #define TX_CFG_MXDMA512 0x00700000
190 #define TX_CFG_MXDMA256 0x00600000
191 #define TX_CFG_MXDMA128 0x00500000
192 #define TX_CFG_MXDMA64 0x00400000
193 #define TX_CFG_MXDMA32 0x00300000
194 #define TX_CFG_MXDMA16 0x00200000
195 #define TX_CFG_MXDMA8 0x00100000
196 #define TX_CFG_MXDMA 0x00700000
198 #define TX_CFG_FLTH_MASK 0x0000ff00
199 #define TX_CFG_DRTH_MASK 0x000000ff
201 /*general purpose I/O control register */
202 #define GPIOR_UNUSED 0xffff8000
203 #define GPIOR_GP5_IN 0x00004000
204 #define GPIOR_GP4_IN 0x00002000
205 #define GPIOR_GP3_IN 0x00001000
206 #define GPIOR_GP2_IN 0x00000800
207 #define GPIOR_GP1_IN 0x00000400
208 #define GPIOR_GP5_OE 0x00000200
209 #define GPIOR_GP4_OE 0x00000100
210 #define GPIOR_GP3_OE 0x00000080
211 #define GPIOR_GP2_OE 0x00000040
212 #define GPIOR_GP1_OE 0x00000020
213 #define GPIOR_GP5_OUT 0x00000010
214 #define GPIOR_GP4_OUT 0x00000008
215 #define GPIOR_GP3_OUT 0x00000004
216 #define GPIOR_GP2_OUT 0x00000002
217 #define GPIOR_GP1_OUT 0x00000001
219 /* receive configuration register */
220 #define RX_CFG_AEP 0x80000000
221 #define RX_CFG_ARP 0x40000000
222 #define RX_CFG_STRIPCRC 0x20000000
223 #define RX_CFG_RX_FD 0x10000000
224 #define RX_CFG_ALP 0x08000000
225 #define RX_CFG_AIRL 0x04000000
226 #define RX_CFG_MXDMA512 0x00700000
227 #define RX_CFG_MXDMA 0x00700000
228 #define RX_CFG_DRTH 0x0000003e
229 #define RX_CFG_DRTH0 0x00000002
231 /* pause control status register */
232 #define PCR_PSEN (1 << 31)
233 #define PCR_PS_MCAST (1 << 30)
234 #define PCR_PS_DA (1 << 29)
235 #define PCR_STHI_8 (3 << 23)
236 #define PCR_STLO_4 (1 << 23)
237 #define PCR_FFHI_8K (3 << 21)
238 #define PCR_FFLO_4K (1 << 21)
239 #define PCR_PAUSE_CNT 0xFFFE
241 /*receive filter/match control register */
242 #define RFCR_RFEN 0x80000000
243 #define RFCR_AAB 0x40000000
244 #define RFCR_AAM 0x20000000
245 #define RFCR_AAU 0x10000000
246 #define RFCR_APM 0x08000000
247 #define RFCR_APAT 0x07800000
248 #define RFCR_APAT3 0x04000000
249 #define RFCR_APAT2 0x02000000
250 #define RFCR_APAT1 0x01000000
251 #define RFCR_APAT0 0x00800000
252 #define RFCR_AARP 0x00400000
253 #define RFCR_MHEN 0x00200000
254 #define RFCR_UHEN 0x00100000
255 #define RFCR_ULM 0x00080000
256 #define RFCR_RFADDR 0x000003ff
258 /* receive filter/match data register */
259 #define RFDR_BMASK 0x00030000
260 #define RFDR_RFDATA0 0x000000ff
261 #define RFDR_RFDATA1 0x0000ff00
263 /* management information base control register */
264 #define MIBC_MIBS 0x00000008
265 #define MIBC_ACLR 0x00000004
266 #define MIBC_FRZ 0x00000002
267 #define MIBC_WRN 0x00000001
269 /* VLAN/IP receive control register */
270 #define VRCR_RUDPE 0x00000080
271 #define VRCR_RTCPE 0x00000040
272 #define VRCR_RIPE 0x00000020
273 #define VRCR_IPEN 0x00000010
274 #define VRCR_DUTF 0x00000008
275 #define VRCR_DVTF 0x00000004
276 #define VRCR_VTREN 0x00000002
277 #define VRCR_VTDEN 0x00000001
279 /* VLAN/IP transmit control register */
280 #define VTCR_PPCHK 0x00000008
281 #define VTCR_GCHK 0x00000004
282 #define VTCR_VPPTI 0x00000002
283 #define VTCR_VGTI 0x00000001
285 /* Clockrun Control/Status Register */
286 #define CCSR_CLKRUN_EN 0x00000001
288 /* TBI control register */
289 #define TBICR_MR_LOOPBACK 0x00004000
290 #define TBICR_MR_AN_ENABLE 0x00001000
291 #define TBICR_MR_RESTART_AN 0x00000200
293 /* TBI status register */
294 #define TBISR_MR_LINK_STATUS 0x00000020
295 #define TBISR_MR_AN_COMPLETE 0x00000004
297 /* TBI auto-negotiation advertisement register */
298 #define TANAR_NP 0x00008000
299 #define TANAR_RF2 0x00002000
300 #define TANAR_RF1 0x00001000
301 #define TANAR_PS2 0x00000100
302 #define TANAR_PS1 0x00000080
303 #define TANAR_HALF_DUP 0x00000040
304 #define TANAR_FULL_DUP 0x00000020
305 #define TANAR_UNUSED 0x00000E1F
307 /* M5 control register */
308 #define M5REG_RESERVED 0xfffffffe
309 #define M5REG_DEDICATED 0x00000001
312 uint32_t link
; /* link field to next descriptor in linked list */
313 uint32_t bufptr
; /* pointer to the first fragment or buffer */
314 uint32_t cmdsts
; /* command/status field */
315 uint32_t extsts
; /* extended status field for VLAN and IP info */
319 uint64_t link
; /* link field to next descriptor in linked list */
320 uint64_t bufptr
; /* pointer to the first fragment or buffer */
321 uint32_t cmdsts
; /* command/status field */
322 uint32_t extsts
; /* extended status field for VLAN and IP info */
325 /* cmdsts flags for descriptors */
326 #define CMDSTS_OWN 0x80000000
327 #define CMDSTS_MORE 0x40000000
328 #define CMDSTS_INTR 0x20000000
329 #define CMDSTS_ERR 0x10000000
330 #define CMDSTS_OK 0x08000000
331 #define CMDSTS_LEN_MASK 0x0000ffff
333 #define CMDSTS_DEST_MASK 0x01800000
334 #define CMDSTS_DEST_SELF 0x00800000
335 #define CMDSTS_DEST_MULTI 0x01000000
337 /* extended flags for descriptors */
338 #define EXTSTS_UDPERR 0x00400000
339 #define EXTSTS_UDPPKT 0x00200000
340 #define EXTSTS_TCPERR 0x00100000
341 #define EXTSTS_TCPPKT 0x00080000
342 #define EXTSTS_IPERR 0x00040000
343 #define EXTSTS_IPPKT 0x00020000
347 #define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0))
349 #endif /* __DEV_NS_GIGE_REG_H__ */