dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36 #include <bitset>
  37
  38 #include "arch/alpha/ev5.hh"
  39 #include "base/trace.hh"
  40 #include "dev/pciconfigall.hh"
  41 #include "dev/pcidev.hh"
  42 #include "dev/pcireg.h"
  43 #include "mem/bus/bus.hh"
  44 #include "mem/bus/pio_interface.hh"
  45 #include "mem/bus/pio_interface_impl.hh"
  46 #include "mem/functional/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/system.hh"
  49
  50 using namespace std;
  51 using namespace TheISA;
  52
  53 PciConfigAll::PciConfigAll(const string &name,
  54                            Addr a, MemoryController *mmu,
  55                            HierParams *hier, Bus *pio_bus, Tick pio_latency)
  56     : PioDevice(name, NULL), addr(a)
  57 {
  58     mmu->add_child(this, RangeSize(addr, size));
  59
  60     if (pio_bus) {
  61         pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
  62                                       &PciConfigAll::cacheAccess);
  63         pioInterface->addAddrRange(RangeSize(addr, size));
  64         pioLatency = pio_latency * pio_bus->clockRate;
  65     }
  66
  67     // Make all the pointers to devices null
  68     for(int x=0; x < MAX_PCI_DEV; x++)
  69         for(int y=0; y < MAX_PCI_FUNC; y++)
  70             devices[x][y] = NULL;
  71 }
  72
  73 // If two interrupts share the same line largely bad things will happen.
  74 // Since we don't track how many times an interrupt was set and correspondingly
  75 // cleared two devices on the same interrupt line and assert and deassert each
  76 // others interrupt "line". Interrupts will not work correctly.
  77 void
  78 PciConfigAll::startup()
  79 {
  80     bitset<256> intLines;
  81     PciDev *tempDev;
  82     uint8_t intline;
  83
  84     for (int x = 0; x < MAX_PCI_DEV; x++) {
  85         for (int y = 0; y < MAX_PCI_FUNC; y++) {
  86            if (devices[x][y] != NULL) {
  87                tempDev = devices[x][y];
  88                intline = tempDev->interruptLine();
  89                if (intLines.test(intline))
  90                    warn("Interrupt line %#X is used multiple times"
  91                         "(You probably want to fix this).\n", (uint32_t)intline);
  92                else
  93                    intLines.set(intline);
  94            } // devices != NULL
  95         } // PCI_FUNC
  96     } // PCI_DEV
  97
  98 }
  99
 100 Fault
 101 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
 102 {
 103
 104     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 105
 106     DPRINTF(PciConfigAll, "read  va=%#x da=%#x size=%d\n",
 107             req->vaddr, daddr, req->size);
 108
 109     int device = (daddr >> 11) & 0x1F;
 110     int func = (daddr >> 8) & 0x7;
 111     int reg = daddr & 0xFF;
 112
 113     if (devices[device][func] == NULL) {
 114         switch (req->size) {
 115            // case sizeof(uint64_t):
 116            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
 117            //     return NoFault;
 118             case sizeof(uint32_t):
 119                 *(uint32_t*)data = 0xFFFFFFFF;
 120                 return NoFault;
 121             case sizeof(uint16_t):
 122                 *(uint16_t*)data = 0xFFFF;
 123                 return NoFault;
 124             case sizeof(uint8_t):
 125                 *(uint8_t*)data = 0xFF;
 126                 return NoFault;
 127             default:
 128                 panic("invalid access size(?) for PCI configspace!\n");
 129         }
 130     } else {
 131         switch (req->size) {
 132             case sizeof(uint32_t):
 133             case sizeof(uint16_t):
 134             case sizeof(uint8_t):
 135                 devices[device][func]->readConfig(reg, req->size, data);
 136                 return NoFault;
 137             default:
 138                 panic("invalid access size(?) for PCI configspace!\n");
 139         }
 140     }
 141
 142     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 143              daddr, req->size);
 144
 145     return NoFault;
 146 }
 147
 148 Fault
 149 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 150 {
 151     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 152
 153     int device = (daddr >> 11) & 0x1F;
 154     int func = (daddr >> 8) & 0x7;
 155     int reg = daddr & 0xFF;
 156
 157     if (devices[device][func] == NULL)
 158         panic("Attempting to write to config space on non-existant device\n");
 159     else if (req->size != sizeof(uint8_t) &&
 160              req->size != sizeof(uint16_t) &&
 161              req->size != sizeof(uint32_t))
 162         panic("invalid access size(?) for PCI configspace!\n");
 163
 164     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 165             req->vaddr, req->size, *(uint32_t*)data);
 166
 167     devices[device][func]->writeConfig(reg, req->size, data);
 168
 169     return NoFault;
 170 }
 171
 172 void
 173 PciConfigAll::serialize(std::ostream &os)
 174 {
 175     /*
 176      * There is no state associated with this object that requires
 177      * serialization.  The only real state are the device pointers
 178      * which are all setup by the constructor of the PciDev class
 179      */
 180 }
 181
 182 void
 183 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 184 {
 185     /*
 186      * There is no state associated with this object that requires
 187      * serialization.  The only real state are the device pointers
 188      * which are all setup by the constructor of the PciDev class
 189      */
 190 }
 191
 192 Tick
 193 PciConfigAll::cacheAccess(MemReqPtr &req)
 194 {
 195     return curTick + pioLatency;
 196 }
 197
 198 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 199
 200 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 201
 202     SimObjectParam<MemoryController *> mmu;
 203     Param<Addr> addr;
 204     Param<Addr> mask;
 205     SimObjectParam<Bus*> pio_bus;
 206     Param<Tick> pio_latency;
 207     SimObjectParam<HierParams *> hier;
 208
 209 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 210
 211 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 212
 213     INIT_PARAM(mmu, "Memory Controller"),
 214     INIT_PARAM(addr, "Device Address"),
 215     INIT_PARAM(mask, "Address Mask"),
 216     INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
 217     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 218     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 219
 220 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 221
 222 CREATE_SIM_OBJECT(PciConfigAll)
 223 {
 224     return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
 225                             pio_latency);
 226 }
 227
 228 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 229
 230 #endif // DOXYGEN_SHOULD_SKIP_THIS