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30 * PCI Configspace implementation
37 #include "base/trace.hh"
38 #include "cpu/exec_context.hh"
39 #include "dev/scsi_ctrl.hh"
40 #include "dev/pciconfigall.hh"
41 #include "dev/pcidev.hh"
42 #include "dev/tsunamireg.h"
43 #include "dev/tsunami.hh"
44 #include "mem/functional_mem/memory_control.hh"
45 #include "sim/builder.hh"
46 #include "sim/system.hh"
50 PCIConfigAll::PCIConfigAll(const string
&name
, Tsunami
*t
,
51 Addr addr
, Addr mask
, MemoryController
*mmu
)
52 : MmapDevice(name
, addr
, mask
, mmu
), tsunami(t
)
54 // Put back pointer in tsunami
55 tsunami
->pciconfig
= this;
57 // Make all the pointers to devices null
58 for(int x
=0; x
< MAX_PCI_DEV
; x
++)
59 for(int y
=0; y
< MAX_PCI_FUNC
; y
++)
64 PCIConfigAll::read(MemReqPtr
&req
, uint8_t *data
)
66 DPRINTF(PCIConfigAll
, "read va=%#x size=%d\n",
67 req
->vaddr
, req
->size
);
69 Addr daddr
= (req
->paddr
& addr_mask
);
71 int device
= (daddr
>> 11) & 0x1F;
72 int func
= (daddr
>> 8) & 0x7;
73 int reg
= daddr
& 0xFF;
75 if (devices
[device
][func
] == NULL
) {
77 // case sizeof(uint64_t):
78 // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
80 case sizeof(uint32_t):
81 *(uint32_t*)data
= 0xFFFFFFFF;
83 case sizeof(uint16_t):
84 *(uint16_t*)data
= 0xFFFF;
87 *(uint8_t*)data
= 0xFF;
90 panic("invalid access size(?) for PCI configspace!\n");
94 case sizeof(uint32_t):
95 case sizeof(uint16_t):
97 devices
[device
][func
]->ReadConfig(reg
, req
->size
, data
);
100 panic("invalid access size(?) for PCI configspace!\n");
104 DPRINTFN("Tsunami PCI Configspace ERROR: read daddr=%#x size=%d\n",
111 PCIConfigAll::write(MemReqPtr
&req
, const uint8_t *data
)
113 Addr daddr
= (req
->paddr
& addr_mask
);
115 int device
= (daddr
>> 11) & 0x1F;
116 int func
= (daddr
>> 8) & 0x7;
117 int reg
= daddr
& 0xFF;
125 if (devices
[device
][func
] == NULL
)
126 panic("Attempting to write to config space on non-existant device\n");
129 case sizeof(uint8_t):
130 byte_value
= *(uint8_t*)data
;
132 case sizeof(uint16_t):
133 half_value
= *(uint16_t*)data
;
135 case sizeof(uint32_t):
136 word_value
= *(uint32_t*)data
;
139 panic("invalid access size(?) for PCI configspace!\n");
143 DPRINTF(PCIConfigAll
, "write - va=%#x size=%d data=%#x\n",
144 req
->vaddr
, req
->size
, word_value
);
146 devices
[device
][func
]->WriteConfig(reg
, req
->size
, word_value
);
152 PCIConfigAll::serialize(std::ostream
&os
)
154 // code should be written
158 PCIConfigAll::unserialize(Checkpoint
*cp
, const std::string
§ion
)
160 //code should be written
163 #ifndef DOXYGEN_SHOULD_SKIP_THIS
165 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll
)
167 SimObjectParam
<Tsunami
*> tsunami
;
168 SimObjectParam
<MemoryController
*> mmu
;
172 END_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll
)
174 BEGIN_INIT_SIM_OBJECT_PARAMS(PCIConfigAll
)
176 INIT_PARAM(tsunami
, "Tsunami"),
177 INIT_PARAM(mmu
, "Memory Controller"),
178 INIT_PARAM(addr
, "Device Address"),
179 INIT_PARAM(mask
, "Address Mask")
181 END_INIT_SIM_OBJECT_PARAMS(PCIConfigAll
)
183 CREATE_SIM_OBJECT(PCIConfigAll
)
185 return new PCIConfigAll(getInstanceName(), tsunami
, addr
, mask
, mmu
);
188 REGISTER_SIM_OBJECT("PCIConfigAll", PCIConfigAll
)
190 #endif // DOXYGEN_SHOULD_SKIP_THIS