2 * Copyright (c) 2003 The Regents of The University of Michigan
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30 * PCI Configspace implementation
37 #include "base/trace.hh"
38 #include "cpu/exec_context.hh"
39 #include "dev/scsi_ctrl.hh"
40 #include "dev/pciconfigall.hh"
41 #include "dev/pcidev.hh"
42 #include "mem/functional_mem/memory_control.hh"
43 #include "sim/builder.hh"
44 #include "sim/system.hh"
48 PciConfigAll::PciConfigAll(const string
&name
, Addr a
,
49 MemoryController
*mmu
)
50 : FunctionalMemory(name
), addr(a
)
52 mmu
->add_child(this, Range
<Addr
>(addr
, addr
+ size
));
54 // Make all the pointers to devices null
55 for(int x
=0; x
< MAX_PCI_DEV
; x
++)
56 for(int y
=0; y
< MAX_PCI_FUNC
; y
++)
61 PciConfigAll::read(MemReqPtr
&req
, uint8_t *data
)
63 DPRINTF(PciConfigAll
, "read va=%#x size=%d\n",
64 req
->vaddr
, req
->size
);
66 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
68 int device
= (daddr
>> 11) & 0x1F;
69 int func
= (daddr
>> 8) & 0x7;
70 int reg
= daddr
& 0xFF;
72 if (devices
[device
][func
] == NULL
) {
74 // case sizeof(uint64_t):
75 // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
77 case sizeof(uint32_t):
78 *(uint32_t*)data
= 0xFFFFFFFF;
80 case sizeof(uint16_t):
81 *(uint16_t*)data
= 0xFFFF;
84 *(uint8_t*)data
= 0xFF;
87 panic("invalid access size(?) for PCI configspace!\n");
91 case sizeof(uint32_t):
92 case sizeof(uint16_t):
94 devices
[device
][func
]->ReadConfig(reg
, req
->size
, data
);
97 panic("invalid access size(?) for PCI configspace!\n");
101 DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
108 PciConfigAll::write(MemReqPtr
&req
, const uint8_t *data
)
110 Addr daddr
= (req
->paddr
- (addr
& PA_IMPL_MASK
));
112 int device
= (daddr
>> 11) & 0x1F;
113 int func
= (daddr
>> 8) & 0x7;
114 int reg
= daddr
& 0xFF;
122 if (devices
[device
][func
] == NULL
)
123 panic("Attempting to write to config space on non-existant device\n");
126 case sizeof(uint8_t):
127 byte_value
= *(uint8_t*)data
;
129 case sizeof(uint16_t):
130 half_value
= *(uint16_t*)data
;
132 case sizeof(uint32_t):
133 word_value
= *(uint32_t*)data
;
136 panic("invalid access size(?) for PCI configspace!\n");
140 DPRINTF(PciConfigAll
, "write - va=%#x size=%d data=%#x\n",
141 req
->vaddr
, req
->size
, word_value
);
143 devices
[device
][func
]->WriteConfig(reg
, req
->size
, word_value
);
149 PciConfigAll::serialize(std::ostream
&os
)
151 // code should be written
155 PciConfigAll::unserialize(Checkpoint
*cp
, const std::string
§ion
)
157 //code should be written
160 #ifndef DOXYGEN_SHOULD_SKIP_THIS
162 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll
)
164 SimObjectParam
<MemoryController
*> mmu
;
168 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll
)
170 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll
)
172 INIT_PARAM(mmu
, "Memory Controller"),
173 INIT_PARAM(addr
, "Device Address"),
174 INIT_PARAM(mask
, "Address Mask")
176 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll
)
178 CREATE_SIM_OBJECT(PciConfigAll
)
180 return new PciConfigAll(getInstanceName(), addr
, mmu
);
183 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll
)
185 #endif // DOXYGEN_SHOULD_SKIP_THIS