2 * Copyright (c) 2004 The Regents of The University of Michigan
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30 * PCI Configspace implementation
38 #include "base/trace.hh"
39 #include "dev/pciconfigall.hh"
40 #include "dev/pcidev.hh"
41 #include "dev/pcireg.h"
42 #include "mem/bus/bus.hh"
43 #include "mem/bus/pio_interface.hh"
44 #include "mem/bus/pio_interface_impl.hh"
45 #include "mem/functional_mem/memory_control.hh"
46 #include "sim/builder.hh"
47 #include "sim/system.hh"
51 PciConfigAll::PciConfigAll(const string
&name
,
52 Addr a
, MemoryController
*mmu
,
53 HierParams
*hier
, Bus
*bus
, Tick pio_latency
)
54 : PioDevice(name
, NULL
), addr(a
)
56 mmu
->add_child(this, RangeSize(addr
, size
));
59 pioInterface
= newPioInterface(name
, hier
, bus
, this,
60 &PciConfigAll::cacheAccess
);
61 pioInterface
->addAddrRange(RangeSize(addr
, size
));
62 pioLatency
= pio_latency
* bus
->clockRatio
;
65 // Make all the pointers to devices null
66 for(int x
=0; x
< MAX_PCI_DEV
; x
++)
67 for(int y
=0; y
< MAX_PCI_FUNC
; y
++)
71 // If two interrupts share the same line largely bad things will happen.
72 // Since we don't track how many times an interrupt was set and correspondingly
73 // cleared two devices on the same interrupt line and assert and deassert each
74 // others interrupt "line". Interrupts will not work correctly.
76 PciConfigAll::startup()
82 for (int x
= 0; x
< MAX_PCI_DEV
; x
++) {
83 for (int y
= 0; y
< MAX_PCI_FUNC
; y
++) {
84 if (devices
[x
][y
] != NULL
) {
85 tempDev
= devices
[x
][y
];
86 intline
= tempDev
->interruptLine();
87 if (intLines
.test(intline
))
88 warn("Interrupt line %#X is used multiple times"
89 "(You probably want to fix this).\n", (uint32_t)intline
);
91 intLines
.set(intline
);
99 PciConfigAll::read(MemReqPtr
&req
, uint8_t *data
)
102 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
104 DPRINTF(PciConfigAll
, "read va=%#x da=%#x size=%d\n",
105 req
->vaddr
, daddr
, req
->size
);
107 int device
= (daddr
>> 11) & 0x1F;
108 int func
= (daddr
>> 8) & 0x7;
109 int reg
= daddr
& 0xFF;
111 if (devices
[device
][func
] == NULL
) {
113 // case sizeof(uint64_t):
114 // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
116 case sizeof(uint32_t):
117 *(uint32_t*)data
= 0xFFFFFFFF;
119 case sizeof(uint16_t):
120 *(uint16_t*)data
= 0xFFFF;
122 case sizeof(uint8_t):
123 *(uint8_t*)data
= 0xFF;
126 panic("invalid access size(?) for PCI configspace!\n");
130 case sizeof(uint32_t):
131 case sizeof(uint16_t):
132 case sizeof(uint8_t):
133 devices
[device
][func
]->ReadConfig(reg
, req
->size
, data
);
136 panic("invalid access size(?) for PCI configspace!\n");
140 DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
147 PciConfigAll::write(MemReqPtr
&req
, const uint8_t *data
)
149 Addr daddr
= (req
->paddr
- (addr
& EV5::PAddrImplMask
));
151 int device
= (daddr
>> 11) & 0x1F;
152 int func
= (daddr
>> 8) & 0x7;
153 int reg
= daddr
& 0xFF;
161 if (devices
[device
][func
] == NULL
)
162 panic("Attempting to write to config space on non-existant device\n");
165 case sizeof(uint8_t):
166 byte_value
= *(uint8_t*)data
;
168 case sizeof(uint16_t):
169 half_value
= *(uint16_t*)data
;
171 case sizeof(uint32_t):
172 word_value
= *(uint32_t*)data
;
175 panic("invalid access size(?) for PCI configspace!\n");
179 DPRINTF(PciConfigAll
, "write - va=%#x size=%d data=%#x\n",
180 req
->vaddr
, req
->size
, word_value
);
182 devices
[device
][func
]->WriteConfig(reg
, req
->size
, word_value
);
188 PciConfigAll::serialize(std::ostream
&os
)
191 * There is no state associated with this object that requires
192 * serialization. The only real state are the device pointers
193 * which are all setup by the constructor of the PciDev class
198 PciConfigAll::unserialize(Checkpoint
*cp
, const std::string
§ion
)
201 * There is no state associated with this object that requires
202 * serialization. The only real state are the device pointers
203 * which are all setup by the constructor of the PciDev class
208 PciConfigAll::cacheAccess(MemReqPtr
&req
)
210 return curTick
+ pioLatency
;
213 #ifndef DOXYGEN_SHOULD_SKIP_THIS
215 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll
)
217 SimObjectParam
<MemoryController
*> mmu
;
220 SimObjectParam
<Bus
*> io_bus
;
221 Param
<Tick
> pio_latency
;
222 SimObjectParam
<HierParams
*> hier
;
224 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll
)
226 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll
)
228 INIT_PARAM(mmu
, "Memory Controller"),
229 INIT_PARAM(addr
, "Device Address"),
230 INIT_PARAM(mask
, "Address Mask"),
231 INIT_PARAM_DFLT(io_bus
, "The IO Bus to attach to", NULL
),
232 INIT_PARAM_DFLT(pio_latency
, "Programmed IO latency in bus cycles", 1),
233 INIT_PARAM_DFLT(hier
, "Hierarchy global variables", &defaultHierParams
)
235 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll
)
237 CREATE_SIM_OBJECT(PciConfigAll
)
239 return new PciConfigAll(getInstanceName(), addr
, mmu
, hier
, io_bus
,
243 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll
)
245 #endif // DOXYGEN_SHOULD_SKIP_THIS