dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "dev/scsi_ctrl.hh"
  40 #include "dev/pciconfigall.hh"
  41 #include "dev/pcidev.hh"
  42 #include "dev/tsunamireg.h"
  43 #include "dev/tsunami.hh"
  44 #include "mem/functional_mem/memory_control.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/system.hh"
  47
  48 using namespace std;
  49
  50 PciConfigAll::PciConfigAll(const string &name, Tsunami *t, Addr a,
  51                            MemoryController *mmu)
  52     : FunctionalMemory(name), addr(a), tsunami(t)
  53 {
  54     mmu->add_child(this, Range<Addr>(addr, addr + size));
  55
  56     // Put back pointer in tsunami
  57     tsunami->pciconfig = this;
  58
  59     // Make all the pointers to devices null
  60     for(int x=0; x < MAX_PCI_DEV; x++)
  61         for(int y=0; y < MAX_PCI_FUNC; y++)
  62           devices[x][y] = NULL;
  63 }
  64
  65 Fault
  66 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
  67 {
  68     DPRINTF(PciConfigAll, "read  va=%#x size=%d\n",
  69             req->vaddr, req->size);
  70
  71     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
  72
  73     int device = (daddr >> 11) & 0x1F;
  74     int func = (daddr >> 8) & 0x7;
  75     int reg = daddr & 0xFF;
  76
  77     if (devices[device][func] == NULL) {
  78         switch (req->size) {
  79            // case sizeof(uint64_t):
  80            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
  81            //     return No_Fault;
  82             case sizeof(uint32_t):
  83                 *(uint32_t*)data = 0xFFFFFFFF;
  84                 return No_Fault;
  85             case sizeof(uint16_t):
  86                 *(uint16_t*)data = 0xFFFF;
  87                 return No_Fault;
  88             case sizeof(uint8_t):
  89                 *(uint8_t*)data = 0xFF;
  90                 return No_Fault;
  91             default:
  92                 panic("invalid access size(?) for PCI configspace!\n");
  93         }
  94     } else {
  95         switch (req->size) {
  96             case sizeof(uint32_t):
  97             case sizeof(uint16_t):
  98             case sizeof(uint8_t):
  99                 devices[device][func]->ReadConfig(reg, req->size, data);
 100                 return No_Fault;
 101             default:
 102                 panic("invalid access size(?) for PCI configspace!\n");
 103         }
 104     }
 105
 106     DPRINTFN("Tsunami PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 107              daddr, req->size);
 108
 109     return No_Fault;
 110 }
 111
 112 Fault
 113 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 114 {
 115     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
 116
 117     int device = (daddr >> 11) & 0x1F;
 118     int func = (daddr >> 8) & 0x7;
 119     int reg = daddr & 0xFF;
 120
 121     union {
 122         uint8_t byte_value;
 123         uint16_t half_value;
 124         uint32_t word_value;
 125     };
 126
 127     if (devices[device][func] == NULL)
 128         panic("Attempting to write to config space on non-existant device\n");
 129     else {
 130             switch (req->size) {
 131             case sizeof(uint8_t):
 132                 byte_value = *(uint8_t*)data;
 133                 break;
 134             case sizeof(uint16_t):
 135                 half_value = *(uint16_t*)data;
 136                 break;
 137             case sizeof(uint32_t):
 138                 word_value = *(uint32_t*)data;
 139                 break;
 140             default:
 141                 panic("invalid access size(?) for PCI configspace!\n");
 142             }
 143     }
 144
 145     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 146             req->vaddr, req->size, word_value);
 147
 148     devices[device][func]->WriteConfig(reg, req->size, word_value);
 149
 150     return No_Fault;
 151 }
 152
 153 void
 154 PciConfigAll::serialize(std::ostream &os)
 155 {
 156     // code should be written
 157 }
 158
 159 void
 160 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 161 {
 162     //code should be written
 163 }
 164
 165 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 166
 167 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 168
 169     SimObjectParam<Tsunami *> tsunami;
 170     SimObjectParam<MemoryController *> mmu;
 171     Param<Addr> addr;
 172     Param<Addr> mask;
 173
 174 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 175
 176 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 177
 178     INIT_PARAM(tsunami, "Tsunami"),
 179     INIT_PARAM(mmu, "Memory Controller"),
 180     INIT_PARAM(addr, "Device Address"),
 181     INIT_PARAM(mask, "Address Mask")
 182
 183 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 184
 185 CREATE_SIM_OBJECT(PciConfigAll)
 186 {
 187     return new PciConfigAll(getInstanceName(), tsunami, addr, mmu);
 188 }
 189
 190 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 191
 192 #endif // DOXYGEN_SHOULD_SKIP_THIS