dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36 #include <bitset>
  37
  38 #include "base/trace.hh"
  39 #include "dev/pciconfigall.hh"
  40 #include "dev/pcidev.hh"
  41 #include "dev/pcireg.h"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/functional_mem/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/system.hh"
  48
  49 using namespace std;
  50
  51 PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
  52                            HierParams *hier, Bus *bus, Tick pio_latency)
  53     : PioDevice(name), addr(a)
  54 {
  55     mmu->add_child(this, RangeSize(addr, size));
  56
  57     if (bus) {
  58         pioInterface = newPioInterface(name, hier, bus, this,
  59                                       &PciConfigAll::cacheAccess);
  60         pioInterface->addAddrRange(RangeSize(addr, size));
  61         pioLatency = pio_latency * bus->clockRatio;
  62     }
  63
  64     // Make all the pointers to devices null
  65     for(int x=0; x < MAX_PCI_DEV; x++)
  66         for(int y=0; y < MAX_PCI_FUNC; y++)
  67           devices[x][y] = NULL;
  68 }
  69
  70 // If two interrupts share the same line largely bad things will happen.
  71 // Since we don't track how many times an interrupt was set and correspondingly
  72 // cleared two devices on the same interrupt line and assert and deassert each
  73 // others interrupt "line". Interrupts will not work correctly.
  74 void
  75 PciConfigAll::startup()
  76 {
  77     bitset<256> intLines;
  78     PciDev *tempDev;
  79     uint8_t intline;
  80
  81     for (int x = 0; x < MAX_PCI_DEV; x++) {
  82         for (int y = 0; y < MAX_PCI_FUNC; y++) {
  83            if (devices[x][y] != NULL) {
  84                tempDev = devices[x][y];
  85                intline = tempDev->interruptLine();
  86                if (intLines.test(intline))
  87                    warn("Interrupt line %#X is used multiple times"
  88                         "(You probably want to fix this).\n", (uint32_t)intline);
  89                else
  90                    intLines.set(intline);
  91            } // devices != NULL
  92         } // PCI_FUNC
  93     } // PCI_DEV
  94
  95 }
  96
  97 Fault
  98 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
  99 {
 100     DPRINTF(PciConfigAll, "read  va=%#x size=%d\n",
 101             req->vaddr, req->size);
 102
 103     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 104
 105     int device = (daddr >> 11) & 0x1F;
 106     int func = (daddr >> 8) & 0x7;
 107     int reg = daddr & 0xFF;
 108
 109     if (devices[device][func] == NULL) {
 110         switch (req->size) {
 111            // case sizeof(uint64_t):
 112            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
 113            //     return No_Fault;
 114             case sizeof(uint32_t):
 115                 *(uint32_t*)data = 0xFFFFFFFF;
 116                 return No_Fault;
 117             case sizeof(uint16_t):
 118                 *(uint16_t*)data = 0xFFFF;
 119                 return No_Fault;
 120             case sizeof(uint8_t):
 121                 *(uint8_t*)data = 0xFF;
 122                 return No_Fault;
 123             default:
 124                 panic("invalid access size(?) for PCI configspace!\n");
 125         }
 126     } else {
 127         switch (req->size) {
 128             case sizeof(uint32_t):
 129             case sizeof(uint16_t):
 130             case sizeof(uint8_t):
 131                 devices[device][func]->ReadConfig(reg, req->size, data);
 132                 return No_Fault;
 133             default:
 134                 panic("invalid access size(?) for PCI configspace!\n");
 135         }
 136     }
 137
 138     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 139              daddr, req->size);
 140
 141     return No_Fault;
 142 }
 143
 144 Fault
 145 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 146 {
 147     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 148
 149     int device = (daddr >> 11) & 0x1F;
 150     int func = (daddr >> 8) & 0x7;
 151     int reg = daddr & 0xFF;
 152
 153     union {
 154         uint8_t byte_value;
 155         uint16_t half_value;
 156         uint32_t word_value;
 157     };
 158
 159     if (devices[device][func] == NULL)
 160         panic("Attempting to write to config space on non-existant device\n");
 161     else {
 162             switch (req->size) {
 163             case sizeof(uint8_t):
 164                 byte_value = *(uint8_t*)data;
 165                 break;
 166             case sizeof(uint16_t):
 167                 half_value = *(uint16_t*)data;
 168                 break;
 169             case sizeof(uint32_t):
 170                 word_value = *(uint32_t*)data;
 171                 break;
 172             default:
 173                 panic("invalid access size(?) for PCI configspace!\n");
 174             }
 175     }
 176
 177     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 178             req->vaddr, req->size, word_value);
 179
 180     devices[device][func]->WriteConfig(reg, req->size, word_value);
 181
 182     return No_Fault;
 183 }
 184
 185 void
 186 PciConfigAll::serialize(std::ostream &os)
 187 {
 188     /*
 189      * There is no state associated with this object that requires
 190      * serialization.  The only real state are the device pointers
 191      * which are all setup by the constructor of the PciDev class
 192      */
 193 }
 194
 195 void
 196 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 197 {
 198     /*
 199      * There is no state associated with this object that requires
 200      * serialization.  The only real state are the device pointers
 201      * which are all setup by the constructor of the PciDev class
 202      */
 203 }
 204
 205 Tick
 206 PciConfigAll::cacheAccess(MemReqPtr &req)
 207 {
 208     return curTick + pioLatency;
 209 }
 210
 211 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 212
 213 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 214
 215     SimObjectParam<MemoryController *> mmu;
 216     Param<Addr> addr;
 217     Param<Addr> mask;
 218     SimObjectParam<Bus*> io_bus;
 219     Param<Tick> pio_latency;
 220     SimObjectParam<HierParams *> hier;
 221
 222 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 223
 224 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 225
 226     INIT_PARAM(mmu, "Memory Controller"),
 227     INIT_PARAM(addr, "Device Address"),
 228     INIT_PARAM(mask, "Address Mask"),
 229     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 230     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 231     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 232
 233 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 234
 235 CREATE_SIM_OBJECT(PciConfigAll)
 236 {
 237     return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
 238                             pio_latency);
 239 }
 240
 241 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 242
 243 #endif // DOXYGEN_SHOULD_SKIP_THIS