dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/pcidev.hh"
  40 #include "mem/bus/bus.hh"
  41 #include "mem/bus/pio_interface.hh"
  42 #include "mem/bus/pio_interface_impl.hh"
  43 #include "mem/functional_mem/memory_control.hh"
  44 #include "sim/builder.hh"
  45 #include "sim/system.hh"
  46
  47 using namespace std;
  48
  49 PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
  50                            HierParams *hier, Bus *bus, Tick pio_latency)
  51     : PioDevice(name), addr(a)
  52 {
  53     mmu->add_child(this, RangeSize(addr, size));
  54
  55     if (bus) {
  56         pioInterface = newPioInterface(name, hier, bus, this,
  57                                       &PciConfigAll::cacheAccess);
  58         pioInterface->addAddrRange(RangeSize(addr, size));
  59         pioLatency = pio_latency * bus->clockRatio;
  60     }
  61
  62     // Make all the pointers to devices null
  63     for(int x=0; x < MAX_PCI_DEV; x++)
  64         for(int y=0; y < MAX_PCI_FUNC; y++)
  65           devices[x][y] = NULL;
  66 }
  67
  68 Fault
  69 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
  70 {
  71     DPRINTF(PciConfigAll, "read  va=%#x size=%d\n",
  72             req->vaddr, req->size);
  73
  74     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
  75
  76     int device = (daddr >> 11) & 0x1F;
  77     int func = (daddr >> 8) & 0x7;
  78     int reg = daddr & 0xFF;
  79
  80     if (devices[device][func] == NULL) {
  81         switch (req->size) {
  82            // case sizeof(uint64_t):
  83            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
  84            //     return No_Fault;
  85             case sizeof(uint32_t):
  86                 *(uint32_t*)data = 0xFFFFFFFF;
  87                 return No_Fault;
  88             case sizeof(uint16_t):
  89                 *(uint16_t*)data = 0xFFFF;
  90                 return No_Fault;
  91             case sizeof(uint8_t):
  92                 *(uint8_t*)data = 0xFF;
  93                 return No_Fault;
  94             default:
  95                 panic("invalid access size(?) for PCI configspace!\n");
  96         }
  97     } else {
  98         switch (req->size) {
  99             case sizeof(uint32_t):
 100             case sizeof(uint16_t):
 101             case sizeof(uint8_t):
 102                 devices[device][func]->ReadConfig(reg, req->size, data);
 103                 return No_Fault;
 104             default:
 105                 panic("invalid access size(?) for PCI configspace!\n");
 106         }
 107     }
 108
 109     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 110              daddr, req->size);
 111
 112     return No_Fault;
 113 }
 114
 115 Fault
 116 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 117 {
 118     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 119
 120     int device = (daddr >> 11) & 0x1F;
 121     int func = (daddr >> 8) & 0x7;
 122     int reg = daddr & 0xFF;
 123
 124     union {
 125         uint8_t byte_value;
 126         uint16_t half_value;
 127         uint32_t word_value;
 128     };
 129
 130     if (devices[device][func] == NULL)
 131         panic("Attempting to write to config space on non-existant device\n");
 132     else {
 133             switch (req->size) {
 134             case sizeof(uint8_t):
 135                 byte_value = *(uint8_t*)data;
 136                 break;
 137             case sizeof(uint16_t):
 138                 half_value = *(uint16_t*)data;
 139                 break;
 140             case sizeof(uint32_t):
 141                 word_value = *(uint32_t*)data;
 142                 break;
 143             default:
 144                 panic("invalid access size(?) for PCI configspace!\n");
 145             }
 146     }
 147
 148     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 149             req->vaddr, req->size, word_value);
 150
 151     devices[device][func]->WriteConfig(reg, req->size, word_value);
 152
 153     return No_Fault;
 154 }
 155
 156 void
 157 PciConfigAll::serialize(std::ostream &os)
 158 {
 159     /*
 160      * There is no state associated with this object that requires
 161      * serialization.  The only real state are the device pointers
 162      * which are all setup by the constructor of the PciDev class
 163      */
 164 }
 165
 166 void
 167 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 168 {
 169     /*
 170      * There is no state associated with this object that requires
 171      * serialization.  The only real state are the device pointers
 172      * which are all setup by the constructor of the PciDev class
 173      */
 174 }
 175
 176 Tick
 177 PciConfigAll::cacheAccess(MemReqPtr &req)
 178 {
 179     return curTick + pioLatency;
 180 }
 181
 182 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 183
 184 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 185
 186     SimObjectParam<MemoryController *> mmu;
 187     Param<Addr> addr;
 188     Param<Addr> mask;
 189     SimObjectParam<Bus*> io_bus;
 190     Param<Tick> pio_latency;
 191     SimObjectParam<HierParams *> hier;
 192
 193 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 194
 195 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 196
 197     INIT_PARAM(mmu, "Memory Controller"),
 198     INIT_PARAM(addr, "Device Address"),
 199     INIT_PARAM(mask, "Address Mask"),
 200     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 201     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 202     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 203
 204 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 205
 206 CREATE_SIM_OBJECT(PciConfigAll)
 207 {
 208     return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
 209                             pio_latency);
 210 }
 211
 212 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 213
 214 #endif // DOXYGEN_SHOULD_SKIP_THIS