dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "dev/pciconfigall.hh"
  39 #include "dev/pcidev.hh"
  40 #include "mem/bus/bus.hh"
  41 #include "mem/bus/pio_interface.hh"
  42 #include "mem/bus/pio_interface_impl.hh"
  43 #include "mem/functional_mem/memory_control.hh"
  44 #include "sim/builder.hh"
  45 #include "sim/system.hh"
  46
  47 using namespace std;
  48
  49 PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
  50                            HierParams *hier, Bus *bus)
  51     : PioDevice(name), addr(a)
  52 {
  53     mmu->add_child(this, Range<Addr>(addr, addr + size));
  54
  55     if (bus) {
  56         pioInterface = newPioInterface(name, hier, bus, this,
  57                                       &PciConfigAll::cacheAccess);
  58         pioInterface->addAddrRange(addr, addr + size - 1);
  59     }
  60
  61     // Make all the pointers to devices null
  62     for(int x=0; x < MAX_PCI_DEV; x++)
  63         for(int y=0; y < MAX_PCI_FUNC; y++)
  64           devices[x][y] = NULL;
  65 }
  66
  67 Fault
  68 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
  69 {
  70     DPRINTF(PciConfigAll, "read  va=%#x size=%d\n",
  71             req->vaddr, req->size);
  72
  73     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
  74
  75     int device = (daddr >> 11) & 0x1F;
  76     int func = (daddr >> 8) & 0x7;
  77     int reg = daddr & 0xFF;
  78
  79     if (devices[device][func] == NULL) {
  80         switch (req->size) {
  81            // case sizeof(uint64_t):
  82            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
  83            //     return No_Fault;
  84             case sizeof(uint32_t):
  85                 *(uint32_t*)data = 0xFFFFFFFF;
  86                 return No_Fault;
  87             case sizeof(uint16_t):
  88                 *(uint16_t*)data = 0xFFFF;
  89                 return No_Fault;
  90             case sizeof(uint8_t):
  91                 *(uint8_t*)data = 0xFF;
  92                 return No_Fault;
  93             default:
  94                 panic("invalid access size(?) for PCI configspace!\n");
  95         }
  96     } else {
  97         switch (req->size) {
  98             case sizeof(uint32_t):
  99             case sizeof(uint16_t):
 100             case sizeof(uint8_t):
 101                 devices[device][func]->ReadConfig(reg, req->size, data);
 102                 return No_Fault;
 103             default:
 104                 panic("invalid access size(?) for PCI configspace!\n");
 105         }
 106     }
 107
 108     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 109              daddr, req->size);
 110
 111     return No_Fault;
 112 }
 113
 114 Fault
 115 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 116 {
 117     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
 118
 119     int device = (daddr >> 11) & 0x1F;
 120     int func = (daddr >> 8) & 0x7;
 121     int reg = daddr & 0xFF;
 122
 123     union {
 124         uint8_t byte_value;
 125         uint16_t half_value;
 126         uint32_t word_value;
 127     };
 128
 129     if (devices[device][func] == NULL)
 130         panic("Attempting to write to config space on non-existant device\n");
 131     else {
 132             switch (req->size) {
 133             case sizeof(uint8_t):
 134                 byte_value = *(uint8_t*)data;
 135                 break;
 136             case sizeof(uint16_t):
 137                 half_value = *(uint16_t*)data;
 138                 break;
 139             case sizeof(uint32_t):
 140                 word_value = *(uint32_t*)data;
 141                 break;
 142             default:
 143                 panic("invalid access size(?) for PCI configspace!\n");
 144             }
 145     }
 146
 147     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 148             req->vaddr, req->size, word_value);
 149
 150     devices[device][func]->WriteConfig(reg, req->size, word_value);
 151
 152     return No_Fault;
 153 }
 154
 155 void
 156 PciConfigAll::serialize(std::ostream &os)
 157 {
 158     /*
 159      * There is no state associated with this object that requires
 160      * serialization.  The only real state are the device pointers
 161      * which are all setup by the constructor of the PciDev class
 162      */
 163 }
 164
 165 void
 166 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 167 {
 168     /*
 169      * There is no state associated with this object that requires
 170      * serialization.  The only real state are the device pointers
 171      * which are all setup by the constructor of the PciDev class
 172      */
 173 }
 174
 175 Tick
 176 PciConfigAll::cacheAccess(MemReqPtr &req)
 177 {
 178     return curTick + 1000;
 179 }
 180
 181 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 182
 183 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 184
 185     SimObjectParam<MemoryController *> mmu;
 186     Param<Addr> addr;
 187     Param<Addr> mask;
 188     SimObjectParam<Bus*> io_bus;
 189     SimObjectParam<HierParams *> hier;
 190
 191 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 192
 193 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 194
 195     INIT_PARAM(mmu, "Memory Controller"),
 196     INIT_PARAM(addr, "Device Address"),
 197     INIT_PARAM(mask, "Address Mask"),
 198     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 199     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 200
 201 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 202
 203 CREATE_SIM_OBJECT(PciConfigAll)
 204 {
 205     return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus);
 206 }
 207
 208 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 209
 210 #endif // DOXYGEN_SHOULD_SKIP_THIS