dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36 #include <bitset>
  37
  38 #include "base/trace.hh"
  39 #include "dev/pciconfigall.hh"
  40 #include "dev/pcidev.hh"
  41 #include "dev/pcireg.h"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/functional/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/system.hh"
  48
  49 using namespace std;
  50
  51 PciConfigAll::PciConfigAll(const string &name,
  52                            Addr a, MemoryController *mmu,
  53                            HierParams *hier, Bus *bus, Tick pio_latency)
  54     : PioDevice(name, NULL), addr(a)
  55 {
  56     mmu->add_child(this, RangeSize(addr, size));
  57
  58     if (bus) {
  59         pioInterface = newPioInterface(name, hier, bus, this,
  60                                       &PciConfigAll::cacheAccess);
  61         pioInterface->addAddrRange(RangeSize(addr, size));
  62         pioLatency = pio_latency * bus->clockRate;
  63     }
  64
  65     // Make all the pointers to devices null
  66     for(int x=0; x < MAX_PCI_DEV; x++)
  67         for(int y=0; y < MAX_PCI_FUNC; y++)
  68           devices[x][y] = NULL;
  69 }
  70
  71 // If two interrupts share the same line largely bad things will happen.
  72 // Since we don't track how many times an interrupt was set and correspondingly
  73 // cleared two devices on the same interrupt line and assert and deassert each
  74 // others interrupt "line". Interrupts will not work correctly.
  75 void
  76 PciConfigAll::startup()
  77 {
  78     bitset<256> intLines;
  79     PciDev *tempDev;
  80     uint8_t intline;
  81
  82     for (int x = 0; x < MAX_PCI_DEV; x++) {
  83         for (int y = 0; y < MAX_PCI_FUNC; y++) {
  84            if (devices[x][y] != NULL) {
  85                tempDev = devices[x][y];
  86                intline = tempDev->interruptLine();
  87                if (intLines.test(intline))
  88                    warn("Interrupt line %#X is used multiple times"
  89                         "(You probably want to fix this).\n", (uint32_t)intline);
  90                else
  91                    intLines.set(intline);
  92            } // devices != NULL
  93         } // PCI_FUNC
  94     } // PCI_DEV
  95
  96 }
  97
  98 Fault
  99 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
 100 {
 101
 102     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 103
 104     DPRINTF(PciConfigAll, "read  va=%#x da=%#x size=%d\n",
 105             req->vaddr, daddr, req->size);
 106
 107     int device = (daddr >> 11) & 0x1F;
 108     int func = (daddr >> 8) & 0x7;
 109     int reg = daddr & 0xFF;
 110
 111     if (devices[device][func] == NULL) {
 112         switch (req->size) {
 113            // case sizeof(uint64_t):
 114            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
 115            //     return No_Fault;
 116             case sizeof(uint32_t):
 117                 *(uint32_t*)data = 0xFFFFFFFF;
 118                 return No_Fault;
 119             case sizeof(uint16_t):
 120                 *(uint16_t*)data = 0xFFFF;
 121                 return No_Fault;
 122             case sizeof(uint8_t):
 123                 *(uint8_t*)data = 0xFF;
 124                 return No_Fault;
 125             default:
 126                 panic("invalid access size(?) for PCI configspace!\n");
 127         }
 128     } else {
 129         switch (req->size) {
 130             case sizeof(uint32_t):
 131             case sizeof(uint16_t):
 132             case sizeof(uint8_t):
 133                 devices[device][func]->ReadConfig(reg, req->size, data);
 134                 return No_Fault;
 135             default:
 136                 panic("invalid access size(?) for PCI configspace!\n");
 137         }
 138     }
 139
 140     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 141              daddr, req->size);
 142
 143     return No_Fault;
 144 }
 145
 146 Fault
 147 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 148 {
 149     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 150
 151     int device = (daddr >> 11) & 0x1F;
 152     int func = (daddr >> 8) & 0x7;
 153     int reg = daddr & 0xFF;
 154
 155     uint32_t word_value = 0;
 156
 157     if (devices[device][func] == NULL)
 158         panic("Attempting to write to config space on non-existant device\n");
 159     else {
 160             switch (req->size) {
 161             case sizeof(uint8_t):
 162                 word_value = *(uint8_t*)data & 0x000000FF;
 163                 break;
 164             case sizeof(uint16_t):
 165                 word_value = *(uint16_t*)data & 0x0000FFFF;
 166                 break;
 167             case sizeof(uint32_t):
 168                 word_value = *(uint32_t*)data;
 169                 break;
 170             default:
 171                 panic("invalid access size(?) for PCI configspace!\n");
 172             }
 173     }
 174
 175     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 176             req->vaddr, req->size, word_value);
 177
 178     devices[device][func]->WriteConfig(reg, req->size, word_value);
 179
 180     return No_Fault;
 181 }
 182
 183 void
 184 PciConfigAll::serialize(std::ostream &os)
 185 {
 186     /*
 187      * There is no state associated with this object that requires
 188      * serialization.  The only real state are the device pointers
 189      * which are all setup by the constructor of the PciDev class
 190      */
 191 }
 192
 193 void
 194 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 195 {
 196     /*
 197      * There is no state associated with this object that requires
 198      * serialization.  The only real state are the device pointers
 199      * which are all setup by the constructor of the PciDev class
 200      */
 201 }
 202
 203 Tick
 204 PciConfigAll::cacheAccess(MemReqPtr &req)
 205 {
 206     return curTick + pioLatency;
 207 }
 208
 209 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 210
 211 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 212
 213     SimObjectParam<MemoryController *> mmu;
 214     Param<Addr> addr;
 215     Param<Addr> mask;
 216     SimObjectParam<Bus*> io_bus;
 217     Param<Tick> pio_latency;
 218     SimObjectParam<HierParams *> hier;
 219
 220 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 221
 222 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 223
 224     INIT_PARAM(mmu, "Memory Controller"),
 225     INIT_PARAM(addr, "Device Address"),
 226     INIT_PARAM(mask, "Address Mask"),
 227     INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
 228     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 229     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 230
 231 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 232
 233 CREATE_SIM_OBJECT(PciConfigAll)
 234 {
 235     return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
 236                             pio_latency);
 237 }
 238
 239 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 240
 241 #endif // DOXYGEN_SHOULD_SKIP_THIS