dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36 #include <bitset>
  37
  38 #include "base/trace.hh"
  39 #include "dev/pciconfigall.hh"
  40 #include "dev/pcidev.hh"
  41 #include "dev/pcireg.h"
  42 #include "mem/bus/bus.hh"
  43 #include "mem/bus/pio_interface.hh"
  44 #include "mem/bus/pio_interface_impl.hh"
  45 #include "mem/functional/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/system.hh"
  48
  49 using namespace std;
  50 using namespace TheISA;
  51
  52 PciConfigAll::PciConfigAll(const string &name,
  53                            Addr a, MemoryController *mmu,
  54                            HierParams *hier, Bus *pio_bus, Tick pio_latency)
  55     : PioDevice(name, NULL), addr(a)
  56 {
  57     mmu->add_child(this, RangeSize(addr, size));
  58
  59     if (pio_bus) {
  60         pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
  61                                       &PciConfigAll::cacheAccess);
  62         pioInterface->addAddrRange(RangeSize(addr, size));
  63         pioLatency = pio_latency * pio_bus->clockRate;
  64     }
  65
  66     // Make all the pointers to devices null
  67     for(int x=0; x < MAX_PCI_DEV; x++)
  68         for(int y=0; y < MAX_PCI_FUNC; y++)
  69             devices[x][y] = NULL;
  70 }
  71
  72 // If two interrupts share the same line largely bad things will happen.
  73 // Since we don't track how many times an interrupt was set and correspondingly
  74 // cleared two devices on the same interrupt line and assert and deassert each
  75 // others interrupt "line". Interrupts will not work correctly.
  76 void
  77 PciConfigAll::startup()
  78 {
  79     bitset<256> intLines;
  80     PciDev *tempDev;
  81     uint8_t intline;
  82
  83     for (int x = 0; x < MAX_PCI_DEV; x++) {
  84         for (int y = 0; y < MAX_PCI_FUNC; y++) {
  85            if (devices[x][y] != NULL) {
  86                tempDev = devices[x][y];
  87                intline = tempDev->interruptLine();
  88                if (intLines.test(intline))
  89                    warn("Interrupt line %#X is used multiple times"
  90                         "(You probably want to fix this).\n", (uint32_t)intline);
  91                else
  92                    intLines.set(intline);
  93            } // devices != NULL
  94         } // PCI_FUNC
  95     } // PCI_DEV
  96
  97 }
  98
  99 Fault *
 100 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
 101 {
 102
 103     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 104
 105     DPRINTF(PciConfigAll, "read  va=%#x da=%#x size=%d\n",
 106             req->vaddr, daddr, req->size);
 107
 108     int device = (daddr >> 11) & 0x1F;
 109     int func = (daddr >> 8) & 0x7;
 110     int reg = daddr & 0xFF;
 111
 112     if (devices[device][func] == NULL) {
 113         switch (req->size) {
 114            // case sizeof(uint64_t):
 115            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
 116            //     return NoFault;
 117             case sizeof(uint32_t):
 118                 *(uint32_t*)data = 0xFFFFFFFF;
 119                 return NoFault;
 120             case sizeof(uint16_t):
 121                 *(uint16_t*)data = 0xFFFF;
 122                 return NoFault;
 123             case sizeof(uint8_t):
 124                 *(uint8_t*)data = 0xFF;
 125                 return NoFault;
 126             default:
 127                 panic("invalid access size(?) for PCI configspace!\n");
 128         }
 129     } else {
 130         switch (req->size) {
 131             case sizeof(uint32_t):
 132             case sizeof(uint16_t):
 133             case sizeof(uint8_t):
 134                 devices[device][func]->readConfig(reg, req->size, data);
 135                 return NoFault;
 136             default:
 137                 panic("invalid access size(?) for PCI configspace!\n");
 138         }
 139     }
 140
 141     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 142              daddr, req->size);
 143
 144     return NoFault;
 145 }
 146
 147 Fault *
 148 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 149 {
 150     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
 151
 152     int device = (daddr >> 11) & 0x1F;
 153     int func = (daddr >> 8) & 0x7;
 154     int reg = daddr & 0xFF;
 155
 156     if (devices[device][func] == NULL)
 157         panic("Attempting to write to config space on non-existant device\n");
 158     else if (req->size != sizeof(uint8_t) &&
 159              req->size != sizeof(uint16_t) &&
 160              req->size != sizeof(uint32_t))
 161         panic("invalid access size(?) for PCI configspace!\n");
 162
 163     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 164             req->vaddr, req->size, *(uint32_t*)data);
 165
 166     devices[device][func]->writeConfig(reg, req->size, data);
 167
 168     return NoFault;
 169 }
 170
 171 void
 172 PciConfigAll::serialize(std::ostream &os)
 173 {
 174     /*
 175      * There is no state associated with this object that requires
 176      * serialization.  The only real state are the device pointers
 177      * which are all setup by the constructor of the PciDev class
 178      */
 179 }
 180
 181 void
 182 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 183 {
 184     /*
 185      * There is no state associated with this object that requires
 186      * serialization.  The only real state are the device pointers
 187      * which are all setup by the constructor of the PciDev class
 188      */
 189 }
 190
 191 Tick
 192 PciConfigAll::cacheAccess(MemReqPtr &req)
 193 {
 194     return curTick + pioLatency;
 195 }
 196
 197 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 198
 199 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 200
 201     SimObjectParam<MemoryController *> mmu;
 202     Param<Addr> addr;
 203     Param<Addr> mask;
 204     SimObjectParam<Bus*> pio_bus;
 205     Param<Tick> pio_latency;
 206     SimObjectParam<HierParams *> hier;
 207
 208 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 209
 210 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 211
 212     INIT_PARAM(mmu, "Memory Controller"),
 213     INIT_PARAM(addr, "Device Address"),
 214     INIT_PARAM(mask, "Address Mask"),
 215     INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
 216     INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
 217     INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 218
 219 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 220
 221 CREATE_SIM_OBJECT(PciConfigAll)
 222 {
 223     return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
 224                             pio_latency);
 225 }
 226
 227 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 228
 229 #endif // DOXYGEN_SHOULD_SKIP_THIS