dev/pciconfigall.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * PCI Configspace implementation
  31  */
  32
  33 #include <deque>
  34 #include <string>
  35 #include <vector>
  36
  37 #include "base/trace.hh"
  38 #include "cpu/exec_context.hh"
  39 #include "dev/scsi_ctrl.hh"
  40 #include "dev/pciconfigall.hh"
  41 #include "dev/pcidev.hh"
  42 #include "mem/functional_mem/memory_control.hh"
  43 #include "sim/builder.hh"
  44 #include "sim/system.hh"
  45
  46 using namespace std;
  47
  48 PciConfigAll::PciConfigAll(const string &name, Addr a,
  49                            MemoryController *mmu)
  50     : FunctionalMemory(name), addr(a)
  51 {
  52     mmu->add_child(this, Range<Addr>(addr, addr + size));
  53
  54     // Make all the pointers to devices null
  55     for(int x=0; x < MAX_PCI_DEV; x++)
  56         for(int y=0; y < MAX_PCI_FUNC; y++)
  57           devices[x][y] = NULL;
  58 }
  59
  60 Fault
  61 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
  62 {
  63     DPRINTF(PciConfigAll, "read  va=%#x size=%d\n",
  64             req->vaddr, req->size);
  65
  66     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
  67
  68     int device = (daddr >> 11) & 0x1F;
  69     int func = (daddr >> 8) & 0x7;
  70     int reg = daddr & 0xFF;
  71
  72     if (devices[device][func] == NULL) {
  73         switch (req->size) {
  74            // case sizeof(uint64_t):
  75            //     *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
  76            //     return No_Fault;
  77             case sizeof(uint32_t):
  78                 *(uint32_t*)data = 0xFFFFFFFF;
  79                 return No_Fault;
  80             case sizeof(uint16_t):
  81                 *(uint16_t*)data = 0xFFFF;
  82                 return No_Fault;
  83             case sizeof(uint8_t):
  84                 *(uint8_t*)data = 0xFF;
  85                 return No_Fault;
  86             default:
  87                 panic("invalid access size(?) for PCI configspace!\n");
  88         }
  89     } else {
  90         switch (req->size) {
  91             case sizeof(uint32_t):
  92             case sizeof(uint16_t):
  93             case sizeof(uint8_t):
  94                 devices[device][func]->ReadConfig(reg, req->size, data);
  95                 return No_Fault;
  96             default:
  97                 panic("invalid access size(?) for PCI configspace!\n");
  98         }
  99     }
 100
 101     DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
 102              daddr, req->size);
 103
 104     return No_Fault;
 105 }
 106
 107 Fault
 108 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 109 {
 110     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK));
 111
 112     int device = (daddr >> 11) & 0x1F;
 113     int func = (daddr >> 8) & 0x7;
 114     int reg = daddr & 0xFF;
 115
 116     union {
 117         uint8_t byte_value;
 118         uint16_t half_value;
 119         uint32_t word_value;
 120     };
 121
 122     if (devices[device][func] == NULL)
 123         panic("Attempting to write to config space on non-existant device\n");
 124     else {
 125             switch (req->size) {
 126             case sizeof(uint8_t):
 127                 byte_value = *(uint8_t*)data;
 128                 break;
 129             case sizeof(uint16_t):
 130                 half_value = *(uint16_t*)data;
 131                 break;
 132             case sizeof(uint32_t):
 133                 word_value = *(uint32_t*)data;
 134                 break;
 135             default:
 136                 panic("invalid access size(?) for PCI configspace!\n");
 137             }
 138     }
 139
 140     DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n",
 141             req->vaddr, req->size, word_value);
 142
 143     devices[device][func]->WriteConfig(reg, req->size, word_value);
 144
 145     return No_Fault;
 146 }
 147
 148 void
 149 PciConfigAll::serialize(std::ostream &os)
 150 {
 151     // code should be written
 152 }
 153
 154 void
 155 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 156 {
 157     //code should be written
 158 }
 159
 160 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 161
 162 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 163
 164     SimObjectParam<MemoryController *> mmu;
 165     Param<Addr> addr;
 166     Param<Addr> mask;
 167
 168 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 169
 170 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 171
 172     INIT_PARAM(mmu, "Memory Controller"),
 173     INIT_PARAM(addr, "Device Address"),
 174     INIT_PARAM(mask, "Address Mask")
 175
 176 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 177
 178 CREATE_SIM_OBJECT(PciConfigAll)
 179 {
 180     return new PciConfigAll(getInstanceName(), addr, mmu);
 181 }
 182
 183 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
 184
 185 #endif // DOXYGEN_SHOULD_SKIP_THIS