dev/pciconfigall.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * @file
  31  * PCI Config space implementation.
  32  */
  33
  34 #ifndef __PCICONFIGALL_HH__
  35 #define __PCICONFIGALL_HH__
  36
  37 #include "dev/pcireg.h"
  38 #include "base/range.hh"
  39 #include "dev/io_device.hh"
  40
  41
  42 static const uint32_t MAX_PCI_DEV = 32;
  43 static const uint32_t MAX_PCI_FUNC = 8;
  44
  45 class PciDev;
  46 class MemoryController;
  47
  48 /**
  49  * PCI Config Space
  50  * All of PCI config space needs to return -1 on Tsunami, except
  51  * the devices that exist. This device maps the entire bus config
  52  * space and passes the requests on to TsunamiPCIDev devices as
  53  * appropriate.
  54  */
  55 class PciConfigAll : public PioDevice
  56 {
  57   private:
  58     Addr addr;
  59     static const Addr size = 0xffffff;
  60
  61     /**
  62       * Pointers to all the devices that are registered with this
  63       * particular config space.
  64       */
  65     PciDev* devices[MAX_PCI_DEV][MAX_PCI_FUNC];
  66
  67   public:
  68     /**
  69      * Constructor for PCIConfigAll
  70      * @param name name of the object
  71      * @param a base address of the write
  72      * @param mmu the memory controller
  73      * @param hier object to store parameters universal the device hierarchy
  74      * @param bus The bus that this device is attached to
  75      */
  76     PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
  77                  HierParams *hier, Bus *bus, Tick pio_latency);
  78
  79
  80     /**
  81      * Check if a device exists.
  82      * @param pcidev PCI device to check
  83      * @param pcifunc PCI function to check
  84      * @return true if device exists, false otherwise
  85      */
  86     bool deviceExists(uint32_t pcidev, uint32_t pcifunc)
  87                      { return devices[pcidev][pcifunc] != NULL ? true : false; }
  88
  89     /**
  90      * Registers a device with the config space object.
  91      * @param pcidev PCI device to register
  92      * @param pcifunc PCI function to register
  93      * @param device device to register
  94      */
  95     void registerDevice(uint8_t pcidev, uint8_t pcifunc, PciDev *device)
  96                         { devices[pcidev][pcifunc] = device; }
  97
  98     /**
  99      * Read something in PCI config space. If the device does not exist
 100      * -1 is returned, if the device does exist its PciDev::ReadConfig (or the
 101      * virtual function that overrides) it is called.
 102      * @param req Contains the address of the field to read.
 103      * @param data Return the field read.
 104      * @return The fault condition of the access.
 105      */
 106     virtual Fault read(MemReqPtr &req, uint8_t *data);
 107
 108     /**
 109      * Write to PCI config spcae. If the device does not exit the simulator
 110      * panics. If it does it is passed on the PciDev::WriteConfig (or the virtual
 111      * function that overrides it).
 112      * @param req Contains the address to write to.
 113      * @param data The data to write.
 114      * @return The fault condition of the access.
 115      */
 116
 117     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 118
 119     /**
 120      * Start up function to check if more than one person is using an interrupt line
 121      * and print a warning if such a case exists
 122      */
 123     virtual void startup();
 124
 125     /**
 126      * Serialize this object to the given output stream.
 127      * @param os The stream to serialize to.
 128      */
 129     virtual void serialize(std::ostream &os);
 130
 131     /**
 132      * Reconstruct the state of this object from a checkpoint.
 133      * @param cp The checkpoint use.
 134      * @param section The section name of this object
 135      */
 136     virtual void unserialize(Checkpoint *cp, const std::string &section);
 137
 138     /**
 139      * Return how long this access will take.
 140      * @param req the memory request to calcuate
 141      * @return Tick when the request is done
 142      */
 143     Tick cacheAccess(MemReqPtr &req);
 144
 145 };
 146
 147 #endif // __PCICONFIGALL_HH__