dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pciconfigall.hh"
  45 #include "mem/functional_mem/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/param.hh"
  48 #include "sim/universe.hh"
  49 #include "dev/tsunamireg.h"
  50
  51 using namespace std;
  52
  53 PciDev::PciDev(const string &name, MemoryController *mmu, PciConfigAll *cf,
  54                PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
  55     : DmaDevice(name), mmu(mmu), configSpace(cf), configData(cd), busNum(bus),
  56       deviceNum(dev), functionNum(func)
  57 {
  58     // copy the config data from the PciConfigData object
  59     if (cd) {
  60         memcpy(config.data, cd->config.data, sizeof(config.data));
  61         memcpy(BARSize, cd->BARSize, sizeof(BARSize));
  62         memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
  63     } else
  64         panic("NULL pointer to configuration data");
  65
  66     // Setup pointer in config space to point to this entry
  67     if (cf->deviceExists(dev,func))
  68         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  69     else
  70         cf->registerDevice(dev, func, this);
  71 }
  72
  73 void
  74 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  75 {
  76     switch(size) {
  77       case sizeof(uint32_t):
  78         memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
  79         DPRINTF(PCIDEV,
  80                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  81                 deviceNum, functionNum, offset, size,
  82                 *(uint32_t*)(config.data + offset));
  83         break;
  84
  85       case sizeof(uint16_t):
  86         memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
  87         DPRINTF(PCIDEV,
  88                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  89                 deviceNum, functionNum, offset, size,
  90                 *(uint16_t*)(config.data + offset));
  91         break;
  92
  93       case sizeof(uint8_t):
  94         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  95         DPRINTF(PCIDEV,
  96                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  97                 deviceNum, functionNum, offset, size,
  98                 (uint16_t)(*(uint8_t*)(config.data + offset)));
  99         break;
 100
 101       default:
 102         panic("Invalid Read Size");
 103     }
 104 }
 105
 106 void
 107 PciDev::WriteConfig(int offset, int size, uint32_t data)
 108 {
 109     uint32_t barnum;
 110
 111     union {
 112         uint8_t byte_value;
 113         uint16_t half_value;
 114         uint32_t word_value;
 115     };
 116     word_value = data;
 117
 118     DPRINTF(PCIDEV,
 119             "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
 120             deviceNum, functionNum, offset, size, word_value);
 121
 122     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 123
 124     switch (size) {
 125       case sizeof(uint8_t): // 1-byte access
 126         switch (offset) {
 127           case PCI0_INTERRUPT_LINE:
 128           case PCI_CACHE_LINE_SIZE:
 129           case PCI_LATENCY_TIMER:
 130             *(uint8_t *)&config.data[offset] = byte_value;
 131             break;
 132
 133           default:
 134             panic("writing to a read only register");
 135         }
 136         break;
 137
 138       case sizeof(uint16_t): // 2-byte access
 139         switch (offset) {
 140           case PCI_COMMAND:
 141           case PCI_STATUS:
 142           case PCI_CACHE_LINE_SIZE:
 143             *(uint16_t *)&config.data[offset] = half_value;
 144             break;
 145
 146           default:
 147             panic("writing to a read only register");
 148         }
 149         break;
 150
 151       case sizeof(uint16_t)+1: // 3-byte access
 152         panic("invalid access size");
 153
 154       case sizeof(uint32_t): // 4-byte access
 155         switch (offset) {
 156           case PCI0_BASE_ADDR0:
 157           case PCI0_BASE_ADDR1:
 158           case PCI0_BASE_ADDR2:
 159           case PCI0_BASE_ADDR3:
 160           case PCI0_BASE_ADDR4:
 161           case PCI0_BASE_ADDR5:
 162             // Writing 0xffffffff to a BAR tells the card to set the
 163             // value of the bar
 164             // to size of memory it needs
 165             if (word_value == 0xffffffff) {
 166                 // This is I/O Space, bottom two bits are read only
 167                 if (config.data[offset] & 0x1) {
 168                     *(uint32_t *)&config.data[offset] =
 169                         ~(BARSize[barnum] - 1) |
 170                         (config.data[offset] & 0x3);
 171                 } else {
 172                     // This is memory space, bottom four bits are read only
 173                     *(uint32_t *)&config.data[offset] =
 174                         ~(BARSize[barnum] - 1) |
 175                         (config.data[offset] & 0xF);
 176                 }
 177             } else {
 178                 // This is I/O Space, bottom two bits are read only
 179                 if(config.data[offset] & 0x1) {
 180                     *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
 181                         (config.data[offset] & 0x3);
 182
 183                     if (word_value & ~0x1) {
 184                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
 185                         Addr base_size = BARSize[barnum]-1;
 186
 187                         // It's never been set
 188                         if (BARAddrs[barnum] == 0)
 189                             mmu->add_child((FunctionalMemory *)this,
 190                                            Range<Addr>(base_addr,
 191                                                        base_addr + base_size));
 192                         else
 193                             mmu->update_child((FunctionalMemory *)this,
 194                                               Range<Addr>(BARAddrs[barnum],
 195                                                           BARAddrs[barnum] +
 196                                                           base_size),
 197                                               Range<Addr>(base_addr,
 198                                                           base_addr +
 199                                                           base_size));
 200
 201                         BARAddrs[barnum] = base_addr;
 202                     }
 203
 204                 } else {
 205                     // This is memory space, bottom four bits are read only
 206                     *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
 207                         (config.data[offset] & 0xF);
 208
 209                     if (word_value & ~0x3) {
 210                         Addr base_addr = (word_value & ~0x3) +
 211                             TSUNAMI_PCI0_MEMORY;
 212
 213                         Addr base_size = BARSize[barnum]-1;
 214
 215                         // It's never been set
 216                         if (BARAddrs[barnum] == 0)
 217                             mmu->add_child((FunctionalMemory *)this,
 218                                            Range<Addr>(base_addr,
 219                                                        base_addr + base_size));
 220                         else
 221                             mmu->update_child((FunctionalMemory *)this,
 222                                               Range<Addr>(BARAddrs[barnum],
 223                                                           BARAddrs[barnum] +
 224                                                           base_size),
 225                                               Range<Addr>(base_addr,
 226                                                           base_addr +
 227                                                           base_size));
 228
 229                         BARAddrs[barnum] = base_addr;
 230                     }
 231                  }
 232             }
 233             break;
 234
 235           case PCI0_ROM_BASE_ADDR:
 236             if (word_value == 0xfffffffe)
 237                 *(uint32_t *)&config.data[offset] = 0xffffffff;
 238             else
 239                 *(uint32_t *)&config.data[offset] = word_value;
 240             break;
 241
 242           case PCI_COMMAND:
 243             // This could also clear some of the error bits in the Status
 244             // register. However they should never get set, so lets ignore
 245             // it for now
 246             *(uint16_t *)&config.data[offset] = half_value;
 247             break;
 248
 249           default:
 250             DPRINTF(PCIDEV, "Writing to a read only register");
 251         }
 252         break;
 253     }
 254 }
 255
 256 void
 257 PciDev::serialize(ostream &os)
 258 {
 259     SERIALIZE_ARRAY(BARSize, 6);
 260     SERIALIZE_ARRAY(BARAddrs, 6);
 261     SERIALIZE_ARRAY(config.data, 64);
 262 }
 263
 264 void
 265 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 266 {
 267     UNSERIALIZE_ARRAY(BARSize, 6);
 268     UNSERIALIZE_ARRAY(BARAddrs, 6);
 269     UNSERIALIZE_ARRAY(config.data, 64);
 270
 271     // Add the MMU mappings for the BARs
 272     for (int i=0; i < 6; i++) {
 273         if (BARAddrs[i] != 0)
 274             mmu->add_child((FunctionalMemory *)this,
 275                            Range<Addr>(BARAddrs[i],
 276                                        BARAddrs[i] +
 277                                        BARSize[i] - 1));
 278     }
 279 }
 280
 281 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 282
 283 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 284
 285     Param<int> VendorID;
 286     Param<int> DeviceID;
 287     Param<int> Command;
 288     Param<int> Status;
 289     Param<int> Revision;
 290     Param<int> ProgIF;
 291     Param<int> SubClassCode;
 292     Param<int> ClassCode;
 293     Param<int> CacheLineSize;
 294     Param<int> LatencyTimer;
 295     Param<int> HeaderType;
 296     Param<int> BIST;
 297     Param<uint32_t> BAR0;
 298     Param<uint32_t> BAR1;
 299     Param<uint32_t> BAR2;
 300     Param<uint32_t> BAR3;
 301     Param<uint32_t> BAR4;
 302     Param<uint32_t> BAR5;
 303     Param<uint32_t> CardbusCIS;
 304     Param<int> SubsystemVendorID;
 305     Param<int> SubsystemID;
 306     Param<uint32_t> ExpansionROM;
 307     Param<int> InterruptLine;
 308     Param<int> InterruptPin;
 309     Param<int> MinimumGrant;
 310     Param<int> MaximumLatency;
 311     Param<uint32_t> BAR0Size;
 312     Param<uint32_t> BAR1Size;
 313     Param<uint32_t> BAR2Size;
 314     Param<uint32_t> BAR3Size;
 315     Param<uint32_t> BAR4Size;
 316     Param<uint32_t> BAR5Size;
 317
 318 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 319
 320 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 321
 322     INIT_PARAM(VendorID, "Vendor ID"),
 323     INIT_PARAM(DeviceID, "Device ID"),
 324     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 325     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 326     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 327     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 328     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 329     INIT_PARAM(ClassCode, "Class Code"),
 330     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 331     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 332     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 333     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 334     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 335     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 336     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 337     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 338     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 339     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 340     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 341     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 342     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 343     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 344     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 345     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 346     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 347     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 348     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 349     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 350     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 351     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 352     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 353     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 354
 355 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 356
 357 CREATE_SIM_OBJECT(PciConfigData)
 358 {
 359     PciConfigData *data = new PciConfigData(getInstanceName());
 360
 361     data->config.hdr.vendor = VendorID;
 362     data->config.hdr.device = DeviceID;
 363     data->config.hdr.command = Command;
 364     data->config.hdr.status = Status;
 365     data->config.hdr.revision = Revision;
 366     data->config.hdr.progIF = ProgIF;
 367     data->config.hdr.subClassCode = SubClassCode;
 368     data->config.hdr.classCode = ClassCode;
 369     data->config.hdr.cacheLineSize = CacheLineSize;
 370     data->config.hdr.latencyTimer = LatencyTimer;
 371     data->config.hdr.headerType = HeaderType;
 372     data->config.hdr.bist = BIST;
 373
 374     data->config.hdr.pci0.baseAddr0 = BAR0;
 375     data->config.hdr.pci0.baseAddr1 = BAR1;
 376     data->config.hdr.pci0.baseAddr2 = BAR2;
 377     data->config.hdr.pci0.baseAddr3 = BAR3;
 378     data->config.hdr.pci0.baseAddr4 = BAR4;
 379     data->config.hdr.pci0.baseAddr5 = BAR5;
 380     data->config.hdr.pci0.cardbusCIS = CardbusCIS;
 381     data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
 382     data->config.hdr.pci0.subsystemID = SubsystemVendorID;
 383     data->config.hdr.pci0.expansionROM = ExpansionROM;
 384     data->config.hdr.pci0.interruptLine = InterruptLine;
 385     data->config.hdr.pci0.interruptPin = InterruptPin;
 386     data->config.hdr.pci0.minimumGrant = MinimumGrant;
 387     data->config.hdr.pci0.maximumLatency = MaximumLatency;
 388
 389     data->BARSize[0] = BAR0Size;
 390     data->BARSize[1] = BAR1Size;
 391     data->BARSize[2] = BAR2Size;
 392     data->BARSize[3] = BAR3Size;
 393     data->BARSize[4] = BAR4Size;
 394     data->BARSize[5] = BAR5Size;
 395
 396     return data;
 397 }
 398
 399 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 400
 401 #endif // DOXYGEN_SHOULD_SKIP_THIS