dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/scsi_ctrl.hh"
  44 #include "dev/pcidev.hh"
  45 #include "dev/pciconfigall.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/param.hh"
  49 #include "sim/universe.hh"
  50
  51 using namespace std;
  52
  53 PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
  54                PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
  55     : MmapDevice(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
  56       Bus(bus), Device(dev), Function(func)
  57 {
  58     // copy the config data from the PciConfigData object
  59     if (cd) {
  60         memcpy(config.data, cd->config.data, sizeof(config.data));
  61         memcpy(BARSize, cd->BARSize, sizeof(BARSize));
  62         memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
  63     } else
  64         panic("NULL pointer to configuration data");
  65
  66     // Setup pointer in config space to point to this entry
  67     if (cf->devices[dev][func] != NULL)
  68         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  69     else
  70         cf->devices[dev][func] = this;
  71 }
  72
  73 void
  74 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  75 {
  76     switch(size) {
  77       case sizeof(uint32_t):
  78         memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
  79         DPRINTF(PCIDEV,
  80                 "read device: %#x function: %#x register: %#x data: %#x\n",
  81                 Device, Function, offset, *(uint32_t*)(config.data + offset));
  82         break;
  83
  84       case sizeof(uint16_t):
  85         memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
  86         DPRINTF(PCIDEV,
  87                 "read device: %#x function: %#x register: %#x data: %#x\n",
  88                 Device, Function, offset, *(uint16_t*)(config.data + offset));
  89         break;
  90
  91       case sizeof(uint8_t):
  92         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  93         printf("data: %#x\n", *(uint8_t*)(config.data + offset));
  94         DPRINTF(PCIDEV,
  95                 "read device: %#x function: %#x register: %#x data: %#x\n",
  96                 Device, Function, offset, *(uint8_t*)(config.data + offset));
  97         break;
  98
  99       default:
 100         panic("Invalid Read Size");
 101     }
 102 }
 103
 104 void
 105 PciDev::WriteConfig(int offset, int size, uint32_t data)
 106 {
 107     uint32_t barnum;
 108
 109     union {
 110         uint8_t byte_value;
 111         uint16_t half_value;
 112         uint32_t word_value;
 113     };
 114     word_value = data;
 115
 116     DPRINTF(PCIDEV,
 117             "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
 118             Device, Function, offset, size, word_value);
 119
 120     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 121
 122     switch (size) {
 123       case sizeof(uint8_t): // 1-byte access
 124         switch (offset) {
 125           case PCI0_INTERRUPT_LINE:
 126           case PCI_CACHE_LINE_SIZE:
 127             *(uint8_t *)&config.data[offset] = byte_value;
 128             break;
 129
 130           default:
 131             panic("writing to a read only register");
 132         }
 133         break;
 134
 135       case sizeof(uint16_t): // 2-byte access
 136         switch (offset) {
 137           case PCI_COMMAND:
 138           case PCI_STATUS:
 139           case PCI_CACHE_LINE_SIZE:
 140             *(uint16_t *)&config.data[offset] = half_value;
 141             break;
 142
 143           default:
 144             panic("writing to a read only register");
 145         }
 146         break;
 147
 148       case sizeof(uint16_t)+1: // 3-byte access
 149         panic("invalid access size");
 150
 151       case sizeof(uint32_t): // 4-byte access
 152         switch (offset) {
 153           case PCI0_BASE_ADDR0:
 154           case PCI0_BASE_ADDR1:
 155           case PCI0_BASE_ADDR2:
 156           case PCI0_BASE_ADDR3:
 157           case PCI0_BASE_ADDR4:
 158           case PCI0_BASE_ADDR5:
 159             // Writing 0xffffffff to a BAR tells the card to set the
 160             // value of the bar
 161             // to size of memory it needs
 162             if (word_value == 0xffffffff) {
 163                 // This is I/O Space, bottom two bits are read only
 164                 if (config.data[offset] & 0x1) {
 165                     *(uint32_t *)&config.data[offset] =
 166                         ~(BARSize[barnum] - 1) |
 167                         (config.data[offset] & 0x3);
 168                 } else {
 169                     // This is memory space, bottom four bits are read only
 170                     *(uint32_t *)&config.data[offset] =
 171                         ~(BARSize[barnum] - 1) |
 172                         (config.data[offset] & 0xF);
 173                 }
 174             } else {
 175                 // This is I/O Space, bottom two bits are read only
 176                 if(config.data[offset] & 0x1) {
 177                     *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
 178                         (config.data[offset] & 0x3);
 179                     if (word_value) {
 180                         // It's never been set
 181                         if (BARAddrs[barnum] == 0)
 182                             AddMapping(word_value, BARSize[barnum]-1, MMU);
 183                         else
 184                             ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
 185                                           word_value, BARSize[barnum]-1, MMU);
 186                         BARAddrs[barnum] = word_value;
 187                     }
 188
 189                 } else {
 190                     // This is memory space, bottom four bits are read only
 191                     *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
 192                         (config.data[offset] & 0xF);
 193                 }
 194             }
 195             break;
 196
 197           case PCI0_ROM_BASE_ADDR:
 198             if (word_value == 0xfffffffe)
 199                 *(uint32_t *)&config.data[offset] = 0xffffffff;
 200             else
 201                 *(uint32_t *)&config.data[offset] = word_value;
 202             break;
 203
 204           case PCI_COMMAND:
 205             // This could also clear some of the error bits in the Status
 206             // register. However they should never get set, so lets ignore
 207             // it for now
 208             *(uint16_t *)&config.data[offset] = half_value;
 209             break;
 210
 211           default:
 212             panic("writing to a read only register");
 213         }
 214         break;
 215     }
 216 }
 217
 218 void
 219 PciDev::serialize(ostream &os)
 220 {
 221     SERIALIZE_ARRAY(config.data, 64);
 222 }
 223
 224 void
 225 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 226 {
 227     UNSERIALIZE_ARRAY(config.data, 64);
 228 }
 229
 230 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 231
 232 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 233
 234     Param<int> VendorID;
 235     Param<int> DeviceID;
 236     Param<int> Command;
 237     Param<int> Status;
 238     Param<int> Revision;
 239     Param<int> ProgIF;
 240     Param<int> SubClassCode;
 241     Param<int> ClassCode;
 242     Param<int> CacheLineSize;
 243     Param<int> LatencyTimer;
 244     Param<int> HeaderType;
 245     Param<int> BIST;
 246     Param<uint32_t> BAR0;
 247     Param<uint32_t> BAR1;
 248     Param<uint32_t> BAR2;
 249     Param<uint32_t> BAR3;
 250     Param<uint32_t> BAR4;
 251     Param<uint32_t> BAR5;
 252     Param<uint32_t> CardbusCIS;
 253     Param<int> SubsystemVendorID;
 254     Param<int> SubsystemID;
 255     Param<uint32_t> ExpansionROM;
 256     Param<int> InterruptLine;
 257     Param<int> InterruptPin;
 258     Param<int> MinimumGrant;
 259     Param<int> MaximumLatency;
 260     Param<uint32_t> BAR0Size;
 261     Param<uint32_t> BAR1Size;
 262     Param<uint32_t> BAR2Size;
 263     Param<uint32_t> BAR3Size;
 264     Param<uint32_t> BAR4Size;
 265     Param<uint32_t> BAR5Size;
 266
 267 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 268
 269 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 270
 271     INIT_PARAM(VendorID, "Vendor ID"),
 272     INIT_PARAM(DeviceID, "Device ID"),
 273     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 274     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 275     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 276     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 277     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 278     INIT_PARAM(ClassCode, "Class Code"),
 279     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 280     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 281     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 282     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 283     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 284     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 285     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 286     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 287     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 288     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 289     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 290     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 291     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 292     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 293     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 294     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 295     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 296     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 297     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 298     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 299     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 300     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 301     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 302     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 303
 304 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 305
 306 CREATE_SIM_OBJECT(PciConfigData)
 307 {
 308     PciConfigData *data = new PciConfigData(getInstanceName());
 309
 310     data->config.hdr.vendor = VendorID;
 311     data->config.hdr.device = DeviceID;
 312     data->config.hdr.command = Command;
 313     data->config.hdr.status = Status;
 314     data->config.hdr.revision = Revision;
 315     data->config.hdr.progIF = ProgIF;
 316     data->config.hdr.subClassCode = SubClassCode;
 317     data->config.hdr.classCode = ClassCode;
 318     data->config.hdr.cacheLineSize = CacheLineSize;
 319     data->config.hdr.latencyTimer = LatencyTimer;
 320     data->config.hdr.headerType = HeaderType;
 321     data->config.hdr.bist = BIST;
 322
 323     data->config.hdr.pci0.baseAddr0 = BAR0;
 324     data->config.hdr.pci0.baseAddr1 = BAR1;
 325     data->config.hdr.pci0.baseAddr2 = BAR2;
 326     data->config.hdr.pci0.baseAddr3 = BAR3;
 327     data->config.hdr.pci0.baseAddr4 = BAR4;
 328     data->config.hdr.pci0.baseAddr5 = BAR5;
 329     data->config.hdr.pci0.cardbusCIS = CardbusCIS;
 330     data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
 331     data->config.hdr.pci0.subsystemID = SubsystemVendorID;
 332     data->config.hdr.pci0.expansionROM = ExpansionROM;
 333     data->config.hdr.pci0.interruptLine = InterruptLine;
 334     data->config.hdr.pci0.interruptPin = InterruptPin;
 335     data->config.hdr.pci0.minimumGrant = MinimumGrant;
 336     data->config.hdr.pci0.maximumLatency = MaximumLatency;
 337
 338     data->BARSize[0] = BAR0Size;
 339     data->BARSize[1] = BAR1Size;
 340     data->BARSize[2] = BAR2Size;
 341     data->BARSize[3] = BAR3Size;
 342     data->BARSize[4] = BAR4Size;
 343     data->BARSize[5] = BAR5Size;
 344
 345     return data;
 346 }
 347
 348 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 349
 350 #endif // DOXYGEN_SHOULD_SKIP_THIS