2b2f54fce81f5eba2a4b061bfbb2b6d303a462f9
2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * A single PCI device configuration space entry.
38 #include "base/inifile.hh"
39 #include "base/misc.hh"
40 #include "base/str.hh" // for to_number
41 #include "base/trace.hh"
42 #include "dev/pciareg.h"
43 #include "dev/scsi_ctrl.hh"
44 #include "dev/pcidev.hh"
45 #include "dev/pciconfigall.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "sim/builder.hh"
48 #include "sim/param.hh"
49 #include "sim/universe.hh"
50 #include "dev/tsunamireg.h"
54 PciDev::PciDev(const string
&name
, MemoryController
*mmu
, PciConfigAll
*cf
,
55 PciConfigData
*cd
, uint32_t bus
, uint32_t dev
, uint32_t func
)
56 : FunctionalMemory(name
), MMU(mmu
), configSpace(cf
), configData(cd
),
57 bus(bus
), device(dev
), function(func
)
59 // copy the config data from the PciConfigData object
61 memcpy(config
.data
, cd
->config
.data
, sizeof(config
.data
));
62 memcpy(BARSize
, cd
->BARSize
, sizeof(BARSize
));
63 memcpy(BARAddrs
, cd
->BARAddrs
, sizeof(BARAddrs
));
65 panic("NULL pointer to configuration data");
67 // Setup pointer in config space to point to this entry
68 if (cf
->devices
[dev
][func
] != NULL
)
69 panic("Two PCI devices occuping same dev: %#x func: %#x", dev
, func
);
71 cf
->devices
[dev
][func
] = this;
75 PciDev::ReadConfig(int offset
, int size
, uint8_t *data
)
78 case sizeof(uint32_t):
79 memcpy((uint32_t*)data
, config
.data
+ offset
, sizeof(uint32_t));
81 "read device: %#x function: %#x register: %#x data: %#x\n",
82 device
, function
, offset
, *(uint32_t*)(config
.data
+ offset
));
85 case sizeof(uint16_t):
86 memcpy((uint16_t*)data
, config
.data
+ offset
, sizeof(uint16_t));
88 "read device: %#x function: %#x register: %#x data: %#x\n",
89 device
, function
, offset
, *(uint16_t*)(config
.data
+ offset
));
93 memcpy((uint8_t*)data
, config
.data
+ offset
, sizeof(uint8_t));
95 "read device: %#x function: %#x register: %#x data: %#x\n",
96 device
, function
, offset
, (uint16_t)(*(uint8_t*)(config
.data
+ offset
)));
100 panic("Invalid Read Size");
105 PciDev::WriteConfig(int offset
, int size
, uint32_t data
)
117 "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
118 device
, function
, offset
, size
, word_value
);
120 barnum
= (offset
- PCI0_BASE_ADDR0
) >> 2;
123 case sizeof(uint8_t): // 1-byte access
125 case PCI0_INTERRUPT_LINE
:
126 case PCI_CACHE_LINE_SIZE
:
127 case PCI_LATENCY_TIMER
:
128 *(uint8_t *)&config
.data
[offset
] = byte_value
;
132 panic("writing to a read only register");
136 case sizeof(uint16_t): // 2-byte access
140 case PCI_CACHE_LINE_SIZE
:
141 *(uint16_t *)&config
.data
[offset
] = half_value
;
145 panic("writing to a read only register");
149 case sizeof(uint16_t)+1: // 3-byte access
150 panic("invalid access size");
152 case sizeof(uint32_t): // 4-byte access
154 case PCI0_BASE_ADDR0
:
155 case PCI0_BASE_ADDR1
:
156 case PCI0_BASE_ADDR2
:
157 case PCI0_BASE_ADDR3
:
158 case PCI0_BASE_ADDR4
:
159 case PCI0_BASE_ADDR5
:
160 // Writing 0xffffffff to a BAR tells the card to set the
162 // to size of memory it needs
163 if (word_value
== 0xffffffff) {
164 // This is I/O Space, bottom two bits are read only
165 if (config
.data
[offset
] & 0x1) {
166 *(uint32_t *)&config
.data
[offset
] =
167 ~(BARSize
[barnum
] - 1) |
168 (config
.data
[offset
] & 0x3);
170 // This is memory space, bottom four bits are read only
171 *(uint32_t *)&config
.data
[offset
] =
172 ~(BARSize
[barnum
] - 1) |
173 (config
.data
[offset
] & 0xF);
176 // This is I/O Space, bottom two bits are read only
177 if(config
.data
[offset
] & 0x1) {
178 *(uint32_t *)&config
.data
[offset
] = (word_value
& ~0x3) |
179 (config
.data
[offset
] & 0x3);
181 if (word_value
& ~0x1) {
182 Addr base_addr
= (word_value
& ~0x1) + TSUNAMI_PCI0_IO
;
183 Addr base_size
= BARSize
[barnum
]-1;
185 // It's never been set
186 if (BARAddrs
[barnum
] == 0)
188 Range
<Addr
>(base_addr
,
189 base_addr
+ base_size
));
191 MMU
->update_child(this,
192 Range
<Addr
>(BARAddrs
[barnum
],
195 Range
<Addr
>(base_addr
,
199 BARAddrs
[barnum
] = base_addr
;
203 // This is memory space, bottom four bits are read only
204 *(uint32_t *)&config
.data
[offset
] = (word_value
& ~0xF) |
205 (config
.data
[offset
] & 0xF);
207 if (word_value
& ~0x3) {
208 Addr base_addr
= (word_value
& ~0x3) +
211 Addr base_size
= BARSize
[barnum
]-1;
213 // It's never been set
214 if (BARAddrs
[barnum
] == 0)
216 Range
<Addr
>(base_addr
,
217 base_addr
+ base_size
));
219 MMU
->update_child(this,
220 Range
<Addr
>(BARAddrs
[barnum
],
223 Range
<Addr
>(base_addr
,
227 BARAddrs
[barnum
] = base_addr
;
233 case PCI0_ROM_BASE_ADDR
:
234 if (word_value
== 0xfffffffe)
235 *(uint32_t *)&config
.data
[offset
] = 0xffffffff;
237 *(uint32_t *)&config
.data
[offset
] = word_value
;
241 // This could also clear some of the error bits in the Status
242 // register. However they should never get set, so lets ignore
244 *(uint16_t *)&config
.data
[offset
] = half_value
;
248 panic("writing to a read only register");
255 PciDev::serialize(ostream
&os
)
257 SERIALIZE_ARRAY(config
.data
, 64);
261 PciDev::unserialize(Checkpoint
*cp
, const std::string
§ion
)
263 UNSERIALIZE_ARRAY(config
.data
, 64);
266 #ifndef DOXYGEN_SHOULD_SKIP_THIS
268 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData
)
276 Param
<int> SubClassCode
;
277 Param
<int> ClassCode
;
278 Param
<int> CacheLineSize
;
279 Param
<int> LatencyTimer
;
280 Param
<int> HeaderType
;
282 Param
<uint32_t> BAR0
;
283 Param
<uint32_t> BAR1
;
284 Param
<uint32_t> BAR2
;
285 Param
<uint32_t> BAR3
;
286 Param
<uint32_t> BAR4
;
287 Param
<uint32_t> BAR5
;
288 Param
<uint32_t> CardbusCIS
;
289 Param
<int> SubsystemVendorID
;
290 Param
<int> SubsystemID
;
291 Param
<uint32_t> ExpansionROM
;
292 Param
<int> InterruptLine
;
293 Param
<int> InterruptPin
;
294 Param
<int> MinimumGrant
;
295 Param
<int> MaximumLatency
;
296 Param
<uint32_t> BAR0Size
;
297 Param
<uint32_t> BAR1Size
;
298 Param
<uint32_t> BAR2Size
;
299 Param
<uint32_t> BAR3Size
;
300 Param
<uint32_t> BAR4Size
;
301 Param
<uint32_t> BAR5Size
;
303 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData
)
305 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData
)
307 INIT_PARAM(VendorID
, "Vendor ID"),
308 INIT_PARAM(DeviceID
, "Device ID"),
309 INIT_PARAM_DFLT(Command
, "Command Register", 0x00),
310 INIT_PARAM_DFLT(Status
, "Status Register", 0x00),
311 INIT_PARAM_DFLT(Revision
, "Device Revision", 0x00),
312 INIT_PARAM_DFLT(ProgIF
, "Programming Interface", 0x00),
313 INIT_PARAM(SubClassCode
, "Sub-Class Code"),
314 INIT_PARAM(ClassCode
, "Class Code"),
315 INIT_PARAM_DFLT(CacheLineSize
, "System Cacheline Size", 0x00),
316 INIT_PARAM_DFLT(LatencyTimer
, "PCI Latency Timer", 0x00),
317 INIT_PARAM_DFLT(HeaderType
, "PCI Header Type", 0x00),
318 INIT_PARAM_DFLT(BIST
, "Built In Self Test", 0x00),
319 INIT_PARAM_DFLT(BAR0
, "Base Address Register 0", 0x00),
320 INIT_PARAM_DFLT(BAR1
, "Base Address Register 1", 0x00),
321 INIT_PARAM_DFLT(BAR2
, "Base Address Register 2", 0x00),
322 INIT_PARAM_DFLT(BAR3
, "Base Address Register 3", 0x00),
323 INIT_PARAM_DFLT(BAR4
, "Base Address Register 4", 0x00),
324 INIT_PARAM_DFLT(BAR5
, "Base Address Register 5", 0x00),
325 INIT_PARAM_DFLT(CardbusCIS
, "Cardbus Card Information Structure", 0x00),
326 INIT_PARAM_DFLT(SubsystemVendorID
, "Subsystem Vendor ID", 0x00),
327 INIT_PARAM_DFLT(SubsystemID
, "Subsystem ID", 0x00),
328 INIT_PARAM_DFLT(ExpansionROM
, "Expansion ROM Base Address Register", 0x00),
329 INIT_PARAM(InterruptLine
, "Interrupt Line Register"),
330 INIT_PARAM(InterruptPin
, "Interrupt Pin Register"),
331 INIT_PARAM_DFLT(MinimumGrant
, "Minimum Grant", 0x00),
332 INIT_PARAM_DFLT(MaximumLatency
, "Maximum Latency", 0x00),
333 INIT_PARAM_DFLT(BAR0Size
, "Base Address Register 0 Size", 0x00),
334 INIT_PARAM_DFLT(BAR1Size
, "Base Address Register 1 Size", 0x00),
335 INIT_PARAM_DFLT(BAR2Size
, "Base Address Register 2 Size", 0x00),
336 INIT_PARAM_DFLT(BAR3Size
, "Base Address Register 3 Size", 0x00),
337 INIT_PARAM_DFLT(BAR4Size
, "Base Address Register 4 Size", 0x00),
338 INIT_PARAM_DFLT(BAR5Size
, "Base Address Register 5 Size", 0x00)
340 END_INIT_SIM_OBJECT_PARAMS(PciConfigData
)
342 CREATE_SIM_OBJECT(PciConfigData
)
344 PciConfigData
*data
= new PciConfigData(getInstanceName());
346 data
->config
.hdr
.vendor
= VendorID
;
347 data
->config
.hdr
.device
= DeviceID
;
348 data
->config
.hdr
.command
= Command
;
349 data
->config
.hdr
.status
= Status
;
350 data
->config
.hdr
.revision
= Revision
;
351 data
->config
.hdr
.progIF
= ProgIF
;
352 data
->config
.hdr
.subClassCode
= SubClassCode
;
353 data
->config
.hdr
.classCode
= ClassCode
;
354 data
->config
.hdr
.cacheLineSize
= CacheLineSize
;
355 data
->config
.hdr
.latencyTimer
= LatencyTimer
;
356 data
->config
.hdr
.headerType
= HeaderType
;
357 data
->config
.hdr
.bist
= BIST
;
359 data
->config
.hdr
.pci0
.baseAddr0
= BAR0
;
360 data
->config
.hdr
.pci0
.baseAddr1
= BAR1
;
361 data
->config
.hdr
.pci0
.baseAddr2
= BAR2
;
362 data
->config
.hdr
.pci0
.baseAddr3
= BAR3
;
363 data
->config
.hdr
.pci0
.baseAddr4
= BAR4
;
364 data
->config
.hdr
.pci0
.baseAddr5
= BAR5
;
365 data
->config
.hdr
.pci0
.cardbusCIS
= CardbusCIS
;
366 data
->config
.hdr
.pci0
.subsystemVendorID
= SubsystemVendorID
;
367 data
->config
.hdr
.pci0
.subsystemID
= SubsystemVendorID
;
368 data
->config
.hdr
.pci0
.expansionROM
= ExpansionROM
;
369 data
->config
.hdr
.pci0
.interruptLine
= InterruptLine
;
370 data
->config
.hdr
.pci0
.interruptPin
= InterruptPin
;
371 data
->config
.hdr
.pci0
.minimumGrant
= MinimumGrant
;
372 data
->config
.hdr
.pci0
.maximumLatency
= MaximumLatency
;
374 data
->BARSize
[0] = BAR0Size
;
375 data
->BARSize
[1] = BAR1Size
;
376 data
->BARSize
[2] = BAR2Size
;
377 data
->BARSize
[3] = BAR3Size
;
378 data
->BARSize
[4] = BAR4Size
;
379 data
->BARSize
[5] = BAR5Size
;
384 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData
)
386 #endif // DOXYGEN_SHOULD_SKIP_THIS