dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/scsi_ctrl.hh"
  44 #include "dev/pcidev.hh"
  45 #include "dev/pciconfigall.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/param.hh"
  49 #include "sim/universe.hh"
  50 #include "dev/tsunamireg.h"
  51
  52 using namespace std;
  53
  54 PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
  55                PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
  56     : MmapDevice(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
  57       Bus(bus), Device(dev), Function(func)
  58 {
  59     // copy the config data from the PciConfigData object
  60     if (cd) {
  61         memcpy(config.data, cd->config.data, sizeof(config.data));
  62         memcpy(BARSize, cd->BARSize, sizeof(BARSize));
  63         memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
  64     } else
  65         panic("NULL pointer to configuration data");
  66
  67     // Setup pointer in config space to point to this entry
  68     if (cf->devices[dev][func] != NULL)
  69         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  70     else
  71         cf->devices[dev][func] = this;
  72 }
  73
  74 void
  75 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  76 {
  77     switch(size) {
  78       case sizeof(uint32_t):
  79         memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
  80         DPRINTF(PCIDEV,
  81                 "read device: %#x function: %#x register: %#x data: %#x\n",
  82                 Device, Function, offset, *(uint32_t*)(config.data + offset));
  83         break;
  84
  85       case sizeof(uint16_t):
  86         memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
  87         DPRINTF(PCIDEV,
  88                 "read device: %#x function: %#x register: %#x data: %#x\n",
  89                 Device, Function, offset, *(uint16_t*)(config.data + offset));
  90         break;
  91
  92       case sizeof(uint8_t):
  93         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  94         printf("data: %#x\n", *(uint8_t*)(config.data + offset));
  95         DPRINTF(PCIDEV,
  96                 "read device: %#x function: %#x register: %#x data: %#x\n",
  97                 Device, Function, offset, *(uint8_t*)(config.data + offset));
  98         break;
  99
 100       default:
 101         panic("Invalid Read Size");
 102     }
 103 }
 104
 105 void
 106 PciDev::WriteConfig(int offset, int size, uint32_t data)
 107 {
 108     uint32_t barnum;
 109
 110     union {
 111         uint8_t byte_value;
 112         uint16_t half_value;
 113         uint32_t word_value;
 114     };
 115     word_value = data;
 116
 117     DPRINTF(PCIDEV,
 118             "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
 119             Device, Function, offset, size, word_value);
 120
 121     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 122
 123     switch (size) {
 124       case sizeof(uint8_t): // 1-byte access
 125         switch (offset) {
 126           case PCI0_INTERRUPT_LINE:
 127           case PCI_CACHE_LINE_SIZE:
 128             *(uint8_t *)&config.data[offset] = byte_value;
 129             break;
 130
 131           default:
 132             panic("writing to a read only register");
 133         }
 134         break;
 135
 136       case sizeof(uint16_t): // 2-byte access
 137         switch (offset) {
 138           case PCI_COMMAND:
 139           case PCI_STATUS:
 140           case PCI_CACHE_LINE_SIZE:
 141             *(uint16_t *)&config.data[offset] = half_value;
 142             break;
 143
 144           default:
 145             panic("writing to a read only register");
 146         }
 147         break;
 148
 149       case sizeof(uint16_t)+1: // 3-byte access
 150         panic("invalid access size");
 151
 152       case sizeof(uint32_t): // 4-byte access
 153         switch (offset) {
 154           case PCI0_BASE_ADDR0:
 155           case PCI0_BASE_ADDR1:
 156           case PCI0_BASE_ADDR2:
 157           case PCI0_BASE_ADDR3:
 158           case PCI0_BASE_ADDR4:
 159           case PCI0_BASE_ADDR5:
 160             // Writing 0xffffffff to a BAR tells the card to set the
 161             // value of the bar
 162             // to size of memory it needs
 163             if (word_value == 0xffffffff) {
 164                 // This is I/O Space, bottom two bits are read only
 165                 if (config.data[offset] & 0x1) {
 166                     *(uint32_t *)&config.data[offset] =
 167                         ~(BARSize[barnum] - 1) |
 168                         (config.data[offset] & 0x3);
 169                 } else {
 170                     // This is memory space, bottom four bits are read only
 171                     *(uint32_t *)&config.data[offset] =
 172                         ~(BARSize[barnum] - 1) |
 173                         (config.data[offset] & 0xF);
 174                 }
 175             } else {
 176                 // This is I/O Space, bottom two bits are read only
 177                 if(config.data[offset] & 0x1) {
 178                     *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
 179                         (config.data[offset] & 0x3);
 180
 181                     if (word_value & ~0x1) {
 182                         // It's never been set
 183                         if (BARAddrs[barnum] == 0)
 184                             AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO,
 185                                        BARSize[barnum]-1, MMU);
 186                         else
 187                             ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
 188                                           (word_value & ~0x1) + TSUNAMI_PCI0_IO,
 189                                           BARSize[barnum]-1, MMU);
 190                         BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
 191                     }
 192
 193                 } else {
 194                     // This is memory space, bottom four bits are read only
 195                     *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
 196                         (config.data[offset] & 0xF);
 197
 198                     if (word_value & ~0x3) {
 199                         // It's never been set
 200                         if (BARAddrs[barnum] == 0)
 201                             AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY,
 202                                        BARSize[barnum]-1, MMU);
 203                         else
 204                             ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1,
 205                                           (word_value & ~0x3) +
 206                                           TSUNAMI_PCI0_MEMORY,
 207                                           BARSize[barnum]-1, MMU);
 208                         BARAddrs[barnum] = (word_value & ~0x3) +
 209                                            TSUNAMI_PCI0_MEMORY;
 210                     }
 211                  }
 212             }
 213             break;
 214
 215           case PCI0_ROM_BASE_ADDR:
 216             if (word_value == 0xfffffffe)
 217                 *(uint32_t *)&config.data[offset] = 0xffffffff;
 218             else
 219                 *(uint32_t *)&config.data[offset] = word_value;
 220             break;
 221
 222           case PCI_COMMAND:
 223             // This could also clear some of the error bits in the Status
 224             // register. However they should never get set, so lets ignore
 225             // it for now
 226             *(uint16_t *)&config.data[offset] = half_value;
 227             break;
 228
 229           default:
 230             panic("writing to a read only register");
 231         }
 232         break;
 233     }
 234 }
 235
 236 void
 237 PciDev::serialize(ostream &os)
 238 {
 239     SERIALIZE_ARRAY(config.data, 64);
 240 }
 241
 242 void
 243 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 244 {
 245     UNSERIALIZE_ARRAY(config.data, 64);
 246 }
 247
 248 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 249
 250 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 251
 252     Param<int> VendorID;
 253     Param<int> DeviceID;
 254     Param<int> Command;
 255     Param<int> Status;
 256     Param<int> Revision;
 257     Param<int> ProgIF;
 258     Param<int> SubClassCode;
 259     Param<int> ClassCode;
 260     Param<int> CacheLineSize;
 261     Param<int> LatencyTimer;
 262     Param<int> HeaderType;
 263     Param<int> BIST;
 264     Param<uint32_t> BAR0;
 265     Param<uint32_t> BAR1;
 266     Param<uint32_t> BAR2;
 267     Param<uint32_t> BAR3;
 268     Param<uint32_t> BAR4;
 269     Param<uint32_t> BAR5;
 270     Param<uint32_t> CardbusCIS;
 271     Param<int> SubsystemVendorID;
 272     Param<int> SubsystemID;
 273     Param<uint32_t> ExpansionROM;
 274     Param<int> InterruptLine;
 275     Param<int> InterruptPin;
 276     Param<int> MinimumGrant;
 277     Param<int> MaximumLatency;
 278     Param<uint32_t> BAR0Size;
 279     Param<uint32_t> BAR1Size;
 280     Param<uint32_t> BAR2Size;
 281     Param<uint32_t> BAR3Size;
 282     Param<uint32_t> BAR4Size;
 283     Param<uint32_t> BAR5Size;
 284
 285 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 286
 287 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 288
 289     INIT_PARAM(VendorID, "Vendor ID"),
 290     INIT_PARAM(DeviceID, "Device ID"),
 291     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 292     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 293     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 294     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 295     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 296     INIT_PARAM(ClassCode, "Class Code"),
 297     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 298     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 299     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 300     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 301     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 302     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 303     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 304     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 305     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 306     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 307     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 308     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 309     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 310     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 311     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 312     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 313     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 314     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 315     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 316     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 317     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 318     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 319     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 320     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 321
 322 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 323
 324 CREATE_SIM_OBJECT(PciConfigData)
 325 {
 326     PciConfigData *data = new PciConfigData(getInstanceName());
 327
 328     data->config.hdr.vendor = VendorID;
 329     data->config.hdr.device = DeviceID;
 330     data->config.hdr.command = Command;
 331     data->config.hdr.status = Status;
 332     data->config.hdr.revision = Revision;
 333     data->config.hdr.progIF = ProgIF;
 334     data->config.hdr.subClassCode = SubClassCode;
 335     data->config.hdr.classCode = ClassCode;
 336     data->config.hdr.cacheLineSize = CacheLineSize;
 337     data->config.hdr.latencyTimer = LatencyTimer;
 338     data->config.hdr.headerType = HeaderType;
 339     data->config.hdr.bist = BIST;
 340
 341     data->config.hdr.pci0.baseAddr0 = BAR0;
 342     data->config.hdr.pci0.baseAddr1 = BAR1;
 343     data->config.hdr.pci0.baseAddr2 = BAR2;
 344     data->config.hdr.pci0.baseAddr3 = BAR3;
 345     data->config.hdr.pci0.baseAddr4 = BAR4;
 346     data->config.hdr.pci0.baseAddr5 = BAR5;
 347     data->config.hdr.pci0.cardbusCIS = CardbusCIS;
 348     data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
 349     data->config.hdr.pci0.subsystemID = SubsystemVendorID;
 350     data->config.hdr.pci0.expansionROM = ExpansionROM;
 351     data->config.hdr.pci0.interruptLine = InterruptLine;
 352     data->config.hdr.pci0.interruptPin = InterruptPin;
 353     data->config.hdr.pci0.minimumGrant = MinimumGrant;
 354     data->config.hdr.pci0.maximumLatency = MaximumLatency;
 355
 356     data->BARSize[0] = BAR0Size;
 357     data->BARSize[1] = BAR1Size;
 358     data->BARSize[2] = BAR2Size;
 359     data->BARSize[3] = BAR3Size;
 360     data->BARSize[4] = BAR4Size;
 361     data->BARSize[5] = BAR5Size;
 362
 363     return data;
 364 }
 365
 366 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 367
 368 #endif // DOXYGEN_SHOULD_SKIP_THIS