850635d49cfc65b01017f68d8077a3b5b1972c6b
2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * A single PCI device configuration space entry.
38 #include "base/inifile.hh"
39 #include "base/misc.hh"
40 #include "base/str.hh" // for to_number
41 #include "base/trace.hh"
42 #include "dev/pciareg.h"
43 #include "dev/pcidev.hh"
44 #include "dev/pciconfigall.hh"
45 #include "mem/bus/bus.hh"
46 #include "mem/functional_mem/memory_control.hh"
47 #include "sim/builder.hh"
48 #include "sim/param.hh"
49 #include "sim/root.hh"
50 #include "dev/tsunamireg.h"
54 PciDev::PciDev(Params
*p
)
55 : DmaDevice(p
->name
, p
->plat
), _params(p
), plat(p
->plat
),
56 configData(p
->configData
)
58 // copy the config data from the PciConfigData object
60 memcpy(config
.data
, configData
->config
.data
, sizeof(config
.data
));
61 memcpy(BARSize
, configData
->BARSize
, sizeof(BARSize
));
62 memcpy(BARAddrs
, configData
->BARAddrs
, sizeof(BARAddrs
));
64 panic("NULL pointer to configuration data");
66 // Setup pointer in config space to point to this entry
67 if (p
->configSpace
->deviceExists(p
->deviceNum
, p
->functionNum
))
68 panic("Two PCI devices occuping same dev: %#x func: %#x",
69 p
->deviceNum
, p
->functionNum
);
71 p
->configSpace
->registerDevice(p
->deviceNum
, p
->functionNum
, this);
75 PciDev::ReadConfig(int offset
, int size
, uint8_t *data
)
77 if (offset
>= PCI_DEVICE_SPECIFIC
)
78 panic("Device specific PCI config space not implemented!\n");
81 case sizeof(uint32_t):
82 memcpy((uint8_t*)data
, config
.data
+ offset
, sizeof(uint32_t));
83 *(uint32_t*)data
= htoa(*(uint32_t*)data
);
85 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
86 params()->deviceNum
, params()->functionNum
, offset
, size
,
87 *(uint32_t*)(config
.data
+ offset
));
90 case sizeof(uint16_t):
91 memcpy((uint8_t*)data
, config
.data
+ offset
, sizeof(uint16_t));
92 *(uint16_t*)data
= htoa(*(uint16_t*)data
);
94 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
95 params()->deviceNum
, params()->functionNum
, offset
, size
,
96 *(uint16_t*)(config
.data
+ offset
));
100 memcpy((uint8_t*)data
, config
.data
+ offset
, sizeof(uint8_t));
102 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
103 params()->deviceNum
, params()->functionNum
, offset
, size
,
104 (uint16_t)(*(uint8_t*)(config
.data
+ offset
)));
108 panic("Invalid Read Size");
113 PciDev::WriteConfig(int offset
, int size
, uint32_t data
)
115 if (offset
>= PCI_DEVICE_SPECIFIC
)
116 panic("Device specific PCI config space not implemented!\n");
128 "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
129 params()->deviceNum
, params()->functionNum
, offset
, size
,
132 barnum
= (offset
- PCI0_BASE_ADDR0
) >> 2;
135 case sizeof(uint8_t): // 1-byte access
137 case PCI0_INTERRUPT_LINE
:
138 case PCI_CACHE_LINE_SIZE
:
139 case PCI_LATENCY_TIMER
:
140 *(uint8_t *)&config
.data
[offset
] = htoa(byte_value
);
144 panic("writing to a read only register");
148 case sizeof(uint16_t): // 2-byte access
152 case PCI_CACHE_LINE_SIZE
:
153 *(uint16_t *)&config
.data
[offset
] = htoa(half_value
);
157 panic("writing to a read only register");
161 case sizeof(uint16_t)+1: // 3-byte access
162 panic("invalid access size");
164 case sizeof(uint32_t): // 4-byte access
166 case PCI0_BASE_ADDR0
:
167 case PCI0_BASE_ADDR1
:
168 case PCI0_BASE_ADDR2
:
169 case PCI0_BASE_ADDR3
:
170 case PCI0_BASE_ADDR4
:
171 case PCI0_BASE_ADDR5
:
172 // Writing 0xffffffff to a BAR tells the card to set the
174 // to size of memory it needs
175 if (word_value
== 0xffffffff) {
176 // This is I/O Space, bottom two bits are read only
177 if (htoa(config
.data
[offset
]) & 0x1) {
178 *(uint32_t *)&config
.data
[offset
] = htoa(
179 ~(BARSize
[barnum
] - 1) |
180 (htoa(config
.data
[offset
]) & 0x3));
182 // This is memory space, bottom four bits are read only
183 *(uint32_t *)&config
.data
[offset
] = htoa(
184 ~(BARSize
[barnum
] - 1) |
185 (htoa(config
.data
[offset
]) & 0xF));
188 MemoryController
*mmu
= params()->mmu
;
190 // This is I/O Space, bottom two bits are read only
191 if(htoa(config
.data
[offset
]) & 0x1) {
192 *(uint32_t *)&config
.data
[offset
] =
193 htoa((word_value
& ~0x3) |
194 (htoa(config
.data
[offset
]) & 0x3));
196 if (word_value
& ~0x1) {
197 Addr base_addr
= (word_value
& ~0x1) + TSUNAMI_PCI0_IO
;
198 Addr base_size
= BARSize
[barnum
];
200 // It's never been set
201 if (BARAddrs
[barnum
] == 0)
202 mmu
->add_child((FunctionalMemory
*)this,
203 RangeSize(base_addr
, base_size
));
205 mmu
->update_child((FunctionalMemory
*)this,
206 RangeSize(BARAddrs
[barnum
],
208 RangeSize(base_addr
, base_size
));
210 BARAddrs
[barnum
] = base_addr
;
214 // This is memory space, bottom four bits are read only
215 *(uint32_t *)&config
.data
[offset
] =
216 htoa((word_value
& ~0xF) |
217 (htoa(config
.data
[offset
]) & 0xF));
219 if (word_value
& ~0x3) {
220 Addr base_addr
= (word_value
& ~0x3) +
223 Addr base_size
= BARSize
[barnum
];
225 // It's never been set
226 if (BARAddrs
[barnum
] == 0)
227 mmu
->add_child((FunctionalMemory
*)this,
228 RangeSize(base_addr
, base_size
));
230 mmu
->update_child((FunctionalMemory
*)this,
231 RangeSize(BARAddrs
[barnum
],
233 RangeSize(base_addr
, base_size
));
235 BARAddrs
[barnum
] = base_addr
;
241 case PCI0_ROM_BASE_ADDR
:
242 if (word_value
== 0xfffffffe)
243 *(uint32_t *)&config
.data
[offset
] = 0xffffffff;
245 *(uint32_t *)&config
.data
[offset
] = htoa(word_value
);
249 // This could also clear some of the error bits in the Status
250 // register. However they should never get set, so lets ignore
252 *(uint16_t *)&config
.data
[offset
] = htoa(half_value
);
256 DPRINTF(PCIDEV
, "Writing to a read only register");
263 PciDev::serialize(ostream
&os
)
265 SERIALIZE_ARRAY(BARSize
, 6);
266 SERIALIZE_ARRAY(BARAddrs
, 6);
267 SERIALIZE_ARRAY(config
.data
, 64);
271 PciDev::unserialize(Checkpoint
*cp
, const std::string
§ion
)
273 UNSERIALIZE_ARRAY(BARSize
, 6);
274 UNSERIALIZE_ARRAY(BARAddrs
, 6);
275 UNSERIALIZE_ARRAY(config
.data
, 64);
277 // Add the MMU mappings for the BARs
278 for (int i
=0; i
< 6; i
++) {
279 if (BARAddrs
[i
] != 0)
280 params()->mmu
->add_child(this, RangeSize(BARAddrs
[i
], BARSize
[i
]));
284 #ifndef DOXYGEN_SHOULD_SKIP_THIS
286 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData
)
288 Param
<uint16_t> VendorID
;
289 Param
<uint16_t> DeviceID
;
290 Param
<uint16_t> Command
;
291 Param
<uint16_t> Status
;
292 Param
<uint8_t> Revision
;
293 Param
<uint8_t> ProgIF
;
294 Param
<uint8_t> SubClassCode
;
295 Param
<uint8_t> ClassCode
;
296 Param
<uint8_t> CacheLineSize
;
297 Param
<uint8_t> LatencyTimer
;
298 Param
<uint8_t> HeaderType
;
300 Param
<uint32_t> BAR0
;
301 Param
<uint32_t> BAR1
;
302 Param
<uint32_t> BAR2
;
303 Param
<uint32_t> BAR3
;
304 Param
<uint32_t> BAR4
;
305 Param
<uint32_t> BAR5
;
306 Param
<uint32_t> CardbusCIS
;
307 Param
<uint16_t> SubsystemVendorID
;
308 Param
<uint16_t> SubsystemID
;
309 Param
<uint32_t> ExpansionROM
;
310 Param
<uint8_t> InterruptLine
;
311 Param
<uint8_t> InterruptPin
;
312 Param
<uint8_t> MinimumGrant
;
313 Param
<uint8_t> MaximumLatency
;
314 Param
<uint32_t> BAR0Size
;
315 Param
<uint32_t> BAR1Size
;
316 Param
<uint32_t> BAR2Size
;
317 Param
<uint32_t> BAR3Size
;
318 Param
<uint32_t> BAR4Size
;
319 Param
<uint32_t> BAR5Size
;
321 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData
)
323 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData
)
325 INIT_PARAM(VendorID
, "Vendor ID"),
326 INIT_PARAM(DeviceID
, "Device ID"),
327 INIT_PARAM_DFLT(Command
, "Command Register", 0x00),
328 INIT_PARAM_DFLT(Status
, "Status Register", 0x00),
329 INIT_PARAM_DFLT(Revision
, "Device Revision", 0x00),
330 INIT_PARAM_DFLT(ProgIF
, "Programming Interface", 0x00),
331 INIT_PARAM(SubClassCode
, "Sub-Class Code"),
332 INIT_PARAM(ClassCode
, "Class Code"),
333 INIT_PARAM_DFLT(CacheLineSize
, "System Cacheline Size", 0x00),
334 INIT_PARAM_DFLT(LatencyTimer
, "PCI Latency Timer", 0x00),
335 INIT_PARAM_DFLT(HeaderType
, "PCI Header Type", 0x00),
336 INIT_PARAM_DFLT(BIST
, "Built In Self Test", 0x00),
337 INIT_PARAM_DFLT(BAR0
, "Base Address Register 0", 0x00),
338 INIT_PARAM_DFLT(BAR1
, "Base Address Register 1", 0x00),
339 INIT_PARAM_DFLT(BAR2
, "Base Address Register 2", 0x00),
340 INIT_PARAM_DFLT(BAR3
, "Base Address Register 3", 0x00),
341 INIT_PARAM_DFLT(BAR4
, "Base Address Register 4", 0x00),
342 INIT_PARAM_DFLT(BAR5
, "Base Address Register 5", 0x00),
343 INIT_PARAM_DFLT(CardbusCIS
, "Cardbus Card Information Structure", 0x00),
344 INIT_PARAM_DFLT(SubsystemVendorID
, "Subsystem Vendor ID", 0x00),
345 INIT_PARAM_DFLT(SubsystemID
, "Subsystem ID", 0x00),
346 INIT_PARAM_DFLT(ExpansionROM
, "Expansion ROM Base Address Register", 0x00),
347 INIT_PARAM(InterruptLine
, "Interrupt Line Register"),
348 INIT_PARAM(InterruptPin
, "Interrupt Pin Register"),
349 INIT_PARAM_DFLT(MinimumGrant
, "Minimum Grant", 0x00),
350 INIT_PARAM_DFLT(MaximumLatency
, "Maximum Latency", 0x00),
351 INIT_PARAM_DFLT(BAR0Size
, "Base Address Register 0 Size", 0x00),
352 INIT_PARAM_DFLT(BAR1Size
, "Base Address Register 1 Size", 0x00),
353 INIT_PARAM_DFLT(BAR2Size
, "Base Address Register 2 Size", 0x00),
354 INIT_PARAM_DFLT(BAR3Size
, "Base Address Register 3 Size", 0x00),
355 INIT_PARAM_DFLT(BAR4Size
, "Base Address Register 4 Size", 0x00),
356 INIT_PARAM_DFLT(BAR5Size
, "Base Address Register 5 Size", 0x00)
358 END_INIT_SIM_OBJECT_PARAMS(PciConfigData
)
360 CREATE_SIM_OBJECT(PciConfigData
)
362 PciConfigData
*data
= new PciConfigData(getInstanceName());
364 data
->config
.hdr
.vendor
= htoa(VendorID
);
365 data
->config
.hdr
.device
= htoa(DeviceID
);
366 data
->config
.hdr
.command
= htoa(Command
);
367 data
->config
.hdr
.status
= htoa(Status
);
368 data
->config
.hdr
.revision
= htoa(Revision
);
369 data
->config
.hdr
.progIF
= htoa(ProgIF
);
370 data
->config
.hdr
.subClassCode
= htoa(SubClassCode
);
371 data
->config
.hdr
.classCode
= htoa(ClassCode
);
372 data
->config
.hdr
.cacheLineSize
= htoa(CacheLineSize
);
373 data
->config
.hdr
.latencyTimer
= htoa(LatencyTimer
);
374 data
->config
.hdr
.headerType
= htoa(HeaderType
);
375 data
->config
.hdr
.bist
= htoa(BIST
);
377 data
->config
.hdr
.pci0
.baseAddr0
= htoa(BAR0
);
378 data
->config
.hdr
.pci0
.baseAddr1
= htoa(BAR1
);
379 data
->config
.hdr
.pci0
.baseAddr2
= htoa(BAR2
);
380 data
->config
.hdr
.pci0
.baseAddr3
= htoa(BAR3
);
381 data
->config
.hdr
.pci0
.baseAddr4
= htoa(BAR4
);
382 data
->config
.hdr
.pci0
.baseAddr5
= htoa(BAR5
);
383 data
->config
.hdr
.pci0
.cardbusCIS
= htoa(CardbusCIS
);
384 data
->config
.hdr
.pci0
.subsystemVendorID
= htoa(SubsystemVendorID
);
385 data
->config
.hdr
.pci0
.subsystemID
= htoa(SubsystemVendorID
);
386 data
->config
.hdr
.pci0
.expansionROM
= htoa(ExpansionROM
);
387 data
->config
.hdr
.pci0
.interruptLine
= htoa(InterruptLine
);
388 data
->config
.hdr
.pci0
.interruptPin
= htoa(InterruptPin
);
389 data
->config
.hdr
.pci0
.minimumGrant
= htoa(MinimumGrant
);
390 data
->config
.hdr
.pci0
.maximumLatency
= htoa(MaximumLatency
);
392 data
->BARSize
[0] = BAR0Size
;
393 data
->BARSize
[1] = BAR1Size
;
394 data
->BARSize
[2] = BAR2Size
;
395 data
->BARSize
[3] = BAR3Size
;
396 data
->BARSize
[4] = BAR4Size
;
397 data
->BARSize
[5] = BAR5Size
;
402 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData
)
404 #endif // DOXYGEN_SHOULD_SKIP_THIS