dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/scsi_ctrl.hh"
  44 #include "dev/pcidev.hh"
  45 #include "dev/pciconfigall.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/param.hh"
  49 #include "sim/universe.hh"
  50 #include "dev/tsunamireg.h"
  51
  52 using namespace std;
  53
  54 PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf,
  55                PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
  56     : FunctionalMemory(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd),
  57       Bus(bus), Device(dev), Function(func)
  58 {
  59     // copy the config data from the PciConfigData object
  60     if (cd) {
  61         memcpy(config.data, cd->config.data, sizeof(config.data));
  62         memcpy(BARSize, cd->BARSize, sizeof(BARSize));
  63         memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
  64     } else
  65         panic("NULL pointer to configuration data");
  66
  67     // Setup pointer in config space to point to this entry
  68     if (cf->devices[dev][func] != NULL)
  69         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  70     else
  71         cf->devices[dev][func] = this;
  72 }
  73
  74 void
  75 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  76 {
  77     switch(size) {
  78       case sizeof(uint32_t):
  79         memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
  80         DPRINTF(PCIDEV,
  81                 "read device: %#x function: %#x register: %#x data: %#x\n",
  82                 Device, Function, offset, *(uint32_t*)(config.data + offset));
  83         break;
  84
  85       case sizeof(uint16_t):
  86         memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
  87         DPRINTF(PCIDEV,
  88                 "read device: %#x function: %#x register: %#x data: %#x\n",
  89                 Device, Function, offset, *(uint16_t*)(config.data + offset));
  90         break;
  91
  92       case sizeof(uint8_t):
  93         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  94         printf("data: %#x\n", *(uint8_t*)(config.data + offset));
  95         DPRINTF(PCIDEV,
  96                 "read device: %#x function: %#x register: %#x data: %#x\n",
  97                 Device, Function, offset, *(uint8_t*)(config.data + offset));
  98         break;
  99
 100       default:
 101         panic("Invalid Read Size");
 102     }
 103 }
 104
 105 void
 106 PciDev::WriteConfig(int offset, int size, uint32_t data)
 107 {
 108     uint32_t barnum;
 109
 110     union {
 111         uint8_t byte_value;
 112         uint16_t half_value;
 113         uint32_t word_value;
 114     };
 115     word_value = data;
 116
 117     DPRINTF(PCIDEV,
 118             "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
 119             Device, Function, offset, size, word_value);
 120
 121     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 122
 123     switch (size) {
 124       case sizeof(uint8_t): // 1-byte access
 125         switch (offset) {
 126           case PCI0_INTERRUPT_LINE:
 127           case PCI_CACHE_LINE_SIZE:
 128           case PCI_LATENCY_TIMER:
 129             *(uint8_t *)&config.data[offset] = byte_value;
 130             break;
 131
 132           default:
 133             panic("writing to a read only register");
 134         }
 135         break;
 136
 137       case sizeof(uint16_t): // 2-byte access
 138         switch (offset) {
 139           case PCI_COMMAND:
 140           case PCI_STATUS:
 141           case PCI_CACHE_LINE_SIZE:
 142             *(uint16_t *)&config.data[offset] = half_value;
 143             break;
 144
 145           default:
 146             panic("writing to a read only register");
 147         }
 148         break;
 149
 150       case sizeof(uint16_t)+1: // 3-byte access
 151         panic("invalid access size");
 152
 153       case sizeof(uint32_t): // 4-byte access
 154         switch (offset) {
 155           case PCI0_BASE_ADDR0:
 156           case PCI0_BASE_ADDR1:
 157           case PCI0_BASE_ADDR2:
 158           case PCI0_BASE_ADDR3:
 159           case PCI0_BASE_ADDR4:
 160           case PCI0_BASE_ADDR5:
 161             // Writing 0xffffffff to a BAR tells the card to set the
 162             // value of the bar
 163             // to size of memory it needs
 164             if (word_value == 0xffffffff) {
 165                 // This is I/O Space, bottom two bits are read only
 166                 if (config.data[offset] & 0x1) {
 167                     *(uint32_t *)&config.data[offset] =
 168                         ~(BARSize[barnum] - 1) |
 169                         (config.data[offset] & 0x3);
 170                 } else {
 171                     // This is memory space, bottom four bits are read only
 172                     *(uint32_t *)&config.data[offset] =
 173                         ~(BARSize[barnum] - 1) |
 174                         (config.data[offset] & 0xF);
 175                 }
 176             } else {
 177                 // This is I/O Space, bottom two bits are read only
 178                 if(config.data[offset] & 0x1) {
 179                     *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
 180                         (config.data[offset] & 0x3);
 181
 182                     if (word_value & ~0x1) {
 183                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
 184                         Addr base_size = BARSize[barnum]-1;
 185
 186                         // It's never been set
 187                         if (BARAddrs[barnum] == 0)
 188                             MMU->add_child(this,
 189                                            Range<Addr>(base_addr,
 190                                                        base_addr + base_size));
 191                         else
 192                             MMU->update_child(this,
 193                                               Range<Addr>(BARAddrs[barnum],
 194                                                           BARAddrs[barnum] +
 195                                                           base_size),
 196                                               Range<Addr>(base_addr,
 197                                                           base_addr +
 198                                                           base_size));
 199
 200                         BARAddrs[barnum] = base_addr;
 201                     }
 202
 203                 } else {
 204                     // This is memory space, bottom four bits are read only
 205                     *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
 206                         (config.data[offset] & 0xF);
 207
 208                     if (word_value & ~0x3) {
 209                         Addr base_addr = (word_value & ~0x3) +
 210                             TSUNAMI_PCI0_MEMORY;
 211
 212                         Addr base_size = BARSize[barnum]-1;
 213
 214                         // It's never been set
 215                         if (BARAddrs[barnum] == 0)
 216                             MMU->add_child(this,
 217                                            Range<Addr>(base_addr,
 218                                                        base_addr + base_size));
 219                         else
 220                             MMU->update_child(this,
 221                                               Range<Addr>(BARAddrs[barnum],
 222                                                           BARAddrs[barnum] +
 223                                                           base_size),
 224                                               Range<Addr>(base_addr,
 225                                                           base_addr +
 226                                                           base_size));
 227
 228                         BARAddrs[barnum] = base_addr;
 229                     }
 230                  }
 231             }
 232             break;
 233
 234           case PCI0_ROM_BASE_ADDR:
 235             if (word_value == 0xfffffffe)
 236                 *(uint32_t *)&config.data[offset] = 0xffffffff;
 237             else
 238                 *(uint32_t *)&config.data[offset] = word_value;
 239             break;
 240
 241           case PCI_COMMAND:
 242             // This could also clear some of the error bits in the Status
 243             // register. However they should never get set, so lets ignore
 244             // it for now
 245             *(uint16_t *)&config.data[offset] = half_value;
 246             break;
 247
 248           default:
 249             panic("writing to a read only register");
 250         }
 251         break;
 252     }
 253 }
 254
 255 void
 256 PciDev::serialize(ostream &os)
 257 {
 258     SERIALIZE_ARRAY(config.data, 64);
 259 }
 260
 261 void
 262 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 263 {
 264     UNSERIALIZE_ARRAY(config.data, 64);
 265 }
 266
 267 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 268
 269 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 270
 271     Param<int> VendorID;
 272     Param<int> DeviceID;
 273     Param<int> Command;
 274     Param<int> Status;
 275     Param<int> Revision;
 276     Param<int> ProgIF;
 277     Param<int> SubClassCode;
 278     Param<int> ClassCode;
 279     Param<int> CacheLineSize;
 280     Param<int> LatencyTimer;
 281     Param<int> HeaderType;
 282     Param<int> BIST;
 283     Param<uint32_t> BAR0;
 284     Param<uint32_t> BAR1;
 285     Param<uint32_t> BAR2;
 286     Param<uint32_t> BAR3;
 287     Param<uint32_t> BAR4;
 288     Param<uint32_t> BAR5;
 289     Param<uint32_t> CardbusCIS;
 290     Param<int> SubsystemVendorID;
 291     Param<int> SubsystemID;
 292     Param<uint32_t> ExpansionROM;
 293     Param<int> InterruptLine;
 294     Param<int> InterruptPin;
 295     Param<int> MinimumGrant;
 296     Param<int> MaximumLatency;
 297     Param<uint32_t> BAR0Size;
 298     Param<uint32_t> BAR1Size;
 299     Param<uint32_t> BAR2Size;
 300     Param<uint32_t> BAR3Size;
 301     Param<uint32_t> BAR4Size;
 302     Param<uint32_t> BAR5Size;
 303
 304 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 305
 306 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 307
 308     INIT_PARAM(VendorID, "Vendor ID"),
 309     INIT_PARAM(DeviceID, "Device ID"),
 310     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 311     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 312     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 313     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 314     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 315     INIT_PARAM(ClassCode, "Class Code"),
 316     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 317     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 318     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 319     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 320     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 321     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 322     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 323     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 324     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 325     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 326     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 327     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 328     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 329     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 330     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 331     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 332     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 333     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 334     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 335     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 336     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 337     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 338     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 339     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 340
 341 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 342
 343 CREATE_SIM_OBJECT(PciConfigData)
 344 {
 345     PciConfigData *data = new PciConfigData(getInstanceName());
 346
 347     data->config.hdr.vendor = VendorID;
 348     data->config.hdr.device = DeviceID;
 349     data->config.hdr.command = Command;
 350     data->config.hdr.status = Status;
 351     data->config.hdr.revision = Revision;
 352     data->config.hdr.progIF = ProgIF;
 353     data->config.hdr.subClassCode = SubClassCode;
 354     data->config.hdr.classCode = ClassCode;
 355     data->config.hdr.cacheLineSize = CacheLineSize;
 356     data->config.hdr.latencyTimer = LatencyTimer;
 357     data->config.hdr.headerType = HeaderType;
 358     data->config.hdr.bist = BIST;
 359
 360     data->config.hdr.pci0.baseAddr0 = BAR0;
 361     data->config.hdr.pci0.baseAddr1 = BAR1;
 362     data->config.hdr.pci0.baseAddr2 = BAR2;
 363     data->config.hdr.pci0.baseAddr3 = BAR3;
 364     data->config.hdr.pci0.baseAddr4 = BAR4;
 365     data->config.hdr.pci0.baseAddr5 = BAR5;
 366     data->config.hdr.pci0.cardbusCIS = CardbusCIS;
 367     data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
 368     data->config.hdr.pci0.subsystemID = SubsystemVendorID;
 369     data->config.hdr.pci0.expansionROM = ExpansionROM;
 370     data->config.hdr.pci0.interruptLine = InterruptLine;
 371     data->config.hdr.pci0.interruptPin = InterruptPin;
 372     data->config.hdr.pci0.minimumGrant = MinimumGrant;
 373     data->config.hdr.pci0.maximumLatency = MaximumLatency;
 374
 375     data->BARSize[0] = BAR0Size;
 376     data->BARSize[1] = BAR1Size;
 377     data->BARSize[2] = BAR2Size;
 378     data->BARSize[3] = BAR3Size;
 379     data->BARSize[4] = BAR4Size;
 380     data->BARSize[5] = BAR5Size;
 381
 382     return data;
 383 }
 384
 385 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 386
 387 #endif // DOXYGEN_SHOULD_SKIP_THIS