dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pcidev.hh"
  43 #include "dev/pciconfigall.hh"
  44 #include "mem/bus/bus.hh"
  45 #include "mem/functional/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/param.hh"
  48 #include "sim/root.hh"
  49 #include "dev/tsunamireg.h"
  50
  51 using namespace std;
  52
  53 PciDev::PciDev(Params *p)
  54     : DmaDevice(p->name, p->plat), _params(p), plat(p->plat),
  55       configData(p->configData)
  56 {
  57     // copy the config data from the PciConfigData object
  58     if (configData) {
  59         memcpy(config.data, configData->config.data, sizeof(config.data));
  60         memcpy(BARSize, configData->BARSize, sizeof(BARSize));
  61         memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
  62     } else
  63         panic("NULL pointer to configuration data");
  64
  65     // Setup pointer in config space to point to this entry
  66     if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
  67         panic("Two PCI devices occuping same dev: %#x func: %#x",
  68               p->deviceNum, p->functionNum);
  69     else
  70         p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
  71 }
  72
  73 Fault *
  74 PciDev::read(MemReqPtr &req, uint8_t *data)
  75 { return NoFault; }
  76
  77 Fault *
  78 PciDev::write(MemReqPtr &req, const uint8_t *data)
  79 { return NoFault; }
  80
  81 Fault *
  82 PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
  83 { panic("not implemented"); }
  84
  85 Fault *
  86 PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
  87 { panic("not implemented"); }
  88
  89 Fault *
  90 PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
  91 { panic("not implemented"); }
  92
  93 Fault *
  94 PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
  95 { panic("not implemented"); }
  96
  97 Fault *
  98 PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
  99 { panic("not implemented"); }
 100
 101 Fault *
 102 PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
 103 { panic("not implemented"); }
 104
 105 Fault *
 106 PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 107 { panic("not implemented"); }
 108
 109 Fault *
 110 PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
 111 { panic("not implemented"); }
 112
 113 Fault *
 114 PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
 115 { panic("not implemented"); }
 116
 117 Fault *
 118 PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
 119 { panic("not implemented"); }
 120
 121 Fault *
 122 PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
 123 { panic("not implemented"); }
 124
 125 Fault *
 126 PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
 127 { panic("not implemented"); }
 128
 129 void
 130 PciDev::readConfig(int offset, int size, uint8_t *data)
 131 {
 132     if (offset >= PCI_DEVICE_SPECIFIC)
 133         panic("Device specific PCI config space not implemented!\n");
 134
 135     switch(size) {
 136       case sizeof(uint8_t):
 137         *data = config.data[offset];
 138         break;
 139       case sizeof(uint16_t):
 140         *(uint16_t*)data = *(uint16_t*)&config.data[offset];
 141         break;
 142       case sizeof(uint32_t):
 143         *(uint32_t*)data = *(uint32_t*)&config.data[offset];
 144         break;
 145       default:
 146         panic("Invalid PCI configuration read size!\n");
 147     }
 148
 149     DPRINTF(PCIDEV,
 150             "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
 151             params()->deviceNum, params()->functionNum, offset, size,
 152             *(uint32_t*)data);
 153 }
 154
 155 void
 156 PciDev::writeConfig(int offset, int size, const uint8_t *data)
 157 {
 158     if (offset >= PCI_DEVICE_SPECIFIC)
 159         panic("Device specific PCI config space not implemented!\n");
 160
 161     uint8_t &data8 = *(uint8_t*)data;
 162     uint16_t &data16 = *(uint16_t*)data;
 163     uint32_t &data32 = *(uint32_t*)data;
 164
 165     DPRINTF(PCIDEV,
 166             "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
 167             params()->deviceNum, params()->functionNum, offset, size, data32);
 168
 169     switch (size) {
 170       case sizeof(uint8_t): // 1-byte access
 171         switch (offset) {
 172           case PCI0_INTERRUPT_LINE:
 173             config.interruptLine = data8;
 174           case PCI_CACHE_LINE_SIZE:
 175             config.cacheLineSize = data8;
 176           case PCI_LATENCY_TIMER:
 177             config.latencyTimer = data8;
 178             break;
 179           /* Do nothing for these read-only registers */
 180           case PCI0_INTERRUPT_PIN:
 181           case PCI0_MINIMUM_GRANT:
 182           case PCI0_MAXIMUM_LATENCY:
 183           case PCI_CLASS_CODE:
 184           case PCI_REVISION_ID:
 185             break;
 186           default:
 187             panic("writing to a read only register");
 188         }
 189         break;
 190
 191       case sizeof(uint16_t): // 2-byte access
 192         switch (offset) {
 193           case PCI_COMMAND:
 194             config.command = data16;
 195           case PCI_STATUS:
 196             config.status = data16;
 197           case PCI_CACHE_LINE_SIZE:
 198             config.cacheLineSize = data16;
 199             break;
 200           default:
 201             panic("writing to a read only register");
 202         }
 203         break;
 204
 205       case sizeof(uint32_t): // 4-byte access
 206         switch (offset) {
 207           case PCI0_BASE_ADDR0:
 208           case PCI0_BASE_ADDR1:
 209           case PCI0_BASE_ADDR2:
 210           case PCI0_BASE_ADDR3:
 211           case PCI0_BASE_ADDR4:
 212           case PCI0_BASE_ADDR5:
 213
 214             uint32_t barnum, bar_mask;
 215             Addr base_addr, base_size, space_base;
 216
 217             barnum = BAR_NUMBER(offset);
 218
 219             if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
 220                 bar_mask = BAR_IO_MASK;
 221                 space_base = TSUNAMI_PCI0_IO;
 222             } else {
 223                 bar_mask = BAR_MEM_MASK;
 224                 space_base = TSUNAMI_PCI0_MEMORY;
 225             }
 226
 227             // Writing 0xffffffff to a BAR tells the card to set the
 228             // value of the bar to size of memory it needs
 229             if (letoh(data32) == 0xffffffff) {
 230                 // This is I/O Space, bottom two bits are read only
 231
 232                 config.baseAddr[barnum] = letoh(
 233                         (~(BARSize[barnum] - 1) & ~bar_mask) |
 234                         (letoh(config.baseAddr[barnum]) & bar_mask));
 235             } else {
 236                 MemoryController *mmu = params()->mmu;
 237
 238                 config.baseAddr[barnum] = letoh(
 239                     (letoh(data32) & ~bar_mask) |
 240                     (letoh(config.baseAddr[barnum]) & bar_mask));
 241
 242                 if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
 243                     base_addr = (letoh(data32) & ~bar_mask) + space_base;
 244                     base_size = BARSize[barnum];
 245
 246                     // It's never been set
 247                     if (BARAddrs[barnum] == 0)
 248                         mmu->add_child((FunctionalMemory *)this,
 249                                        RangeSize(base_addr, base_size));
 250                     else
 251                         mmu->update_child((FunctionalMemory *)this,
 252                                           RangeSize(BARAddrs[barnum], base_size),
 253                                           RangeSize(base_addr, base_size));
 254
 255                     BARAddrs[barnum] = base_addr;
 256                 }
 257             }
 258             break;
 259
 260           case PCI0_ROM_BASE_ADDR:
 261             if (letoh(data32) == 0xfffffffe)
 262                 config.expansionROM = htole((uint32_t)0xffffffff);
 263             else
 264                 config.expansionROM = data32;
 265             break;
 266
 267           case PCI_COMMAND:
 268             // This could also clear some of the error bits in the Status
 269             // register. However they should never get set, so lets ignore
 270             // it for now
 271             config.command = data16;
 272             break;
 273
 274           default:
 275             DPRINTF(PCIDEV, "Writing to a read only register");
 276         }
 277         break;
 278
 279       default:
 280         panic("invalid access size");
 281     }
 282 }
 283
 284 void
 285 PciDev::serialize(ostream &os)
 286 {
 287     SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
 288     SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
 289     SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
 290 }
 291
 292 void
 293 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 294 {
 295     UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
 296     UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
 297     UNSERIALIZE_ARRAY(config.data,
 298                       sizeof(config.data) / sizeof(config.data[0]));
 299
 300     // Add the MMU mappings for the BARs
 301     for (int i=0; i < 6; i++) {
 302         if (BARAddrs[i] != 0)
 303             params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
 304     }
 305 }
 306
 307 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 308
 309 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 310
 311     Param<uint16_t> VendorID;
 312     Param<uint16_t> DeviceID;
 313     Param<uint16_t> Command;
 314     Param<uint16_t> Status;
 315     Param<uint8_t> Revision;
 316     Param<uint8_t> ProgIF;
 317     Param<uint8_t> SubClassCode;
 318     Param<uint8_t> ClassCode;
 319     Param<uint8_t> CacheLineSize;
 320     Param<uint8_t> LatencyTimer;
 321     Param<uint8_t> HeaderType;
 322     Param<uint8_t> BIST;
 323     Param<uint32_t> BAR0;
 324     Param<uint32_t> BAR1;
 325     Param<uint32_t> BAR2;
 326     Param<uint32_t> BAR3;
 327     Param<uint32_t> BAR4;
 328     Param<uint32_t> BAR5;
 329     Param<uint32_t> CardbusCIS;
 330     Param<uint16_t> SubsystemVendorID;
 331     Param<uint16_t> SubsystemID;
 332     Param<uint32_t> ExpansionROM;
 333     Param<uint8_t> InterruptLine;
 334     Param<uint8_t> InterruptPin;
 335     Param<uint8_t> MinimumGrant;
 336     Param<uint8_t> MaximumLatency;
 337     Param<uint32_t> BAR0Size;
 338     Param<uint32_t> BAR1Size;
 339     Param<uint32_t> BAR2Size;
 340     Param<uint32_t> BAR3Size;
 341     Param<uint32_t> BAR4Size;
 342     Param<uint32_t> BAR5Size;
 343
 344 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 345
 346 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 347
 348     INIT_PARAM(VendorID, "Vendor ID"),
 349     INIT_PARAM(DeviceID, "Device ID"),
 350     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 351     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 352     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 353     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 354     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 355     INIT_PARAM(ClassCode, "Class Code"),
 356     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 357     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 358     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 359     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 360     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 361     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 362     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 363     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 364     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 365     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 366     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 367     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 368     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 369     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 370     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 371     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 372     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 373     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 374     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 375     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 376     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 377     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 378     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 379     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 380
 381 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 382
 383 CREATE_SIM_OBJECT(PciConfigData)
 384 {
 385     PciConfigData *data = new PciConfigData(getInstanceName());
 386
 387     data->config.vendor = htole(VendorID);
 388     data->config.device = htole(DeviceID);
 389     data->config.command = htole(Command);
 390     data->config.status = htole(Status);
 391     data->config.revision = htole(Revision);
 392     data->config.progIF = htole(ProgIF);
 393     data->config.subClassCode = htole(SubClassCode);
 394     data->config.classCode = htole(ClassCode);
 395     data->config.cacheLineSize = htole(CacheLineSize);
 396     data->config.latencyTimer = htole(LatencyTimer);
 397     data->config.headerType = htole(HeaderType);
 398     data->config.bist = htole(BIST);
 399
 400     data->config.baseAddr0 = htole(BAR0);
 401     data->config.baseAddr1 = htole(BAR1);
 402     data->config.baseAddr2 = htole(BAR2);
 403     data->config.baseAddr3 = htole(BAR3);
 404     data->config.baseAddr4 = htole(BAR4);
 405     data->config.baseAddr5 = htole(BAR5);
 406     data->config.cardbusCIS = htole(CardbusCIS);
 407     data->config.subsystemVendorID = htole(SubsystemVendorID);
 408     data->config.subsystemID = htole(SubsystemVendorID);
 409     data->config.expansionROM = htole(ExpansionROM);
 410     data->config.interruptLine = htole(InterruptLine);
 411     data->config.interruptPin = htole(InterruptPin);
 412     data->config.minimumGrant = htole(MinimumGrant);
 413     data->config.maximumLatency = htole(MaximumLatency);
 414
 415     data->BARSize[0] = BAR0Size;
 416     data->BARSize[1] = BAR1Size;
 417     data->BARSize[2] = BAR2Size;
 418     data->BARSize[3] = BAR3Size;
 419     data->BARSize[4] = BAR4Size;
 420     data->BARSize[5] = BAR5Size;
 421
 422     return data;
 423 }
 424
 425 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 426
 427 #endif // DOXYGEN_SHOULD_SKIP_THIS