dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/pcidev.hh"
  44 #include "dev/pciconfigall.hh"
  45 #include "mem/functional_mem/memory_control.hh"
  46 #include "sim/builder.hh"
  47 #include "sim/param.hh"
  48 #include "sim/universe.hh"
  49 #include "dev/tsunamireg.h"
  50
  51 using namespace std;
  52
  53 PciDev::PciDev(const string &name, MemoryController *mmu, PciConfigAll *cf,
  54                PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func)
  55     : DmaDevice(name), mmu(mmu), configSpace(cf), configData(cd), busNum(bus),
  56       deviceNum(dev), functionNum(func)
  57 {
  58     // copy the config data from the PciConfigData object
  59     if (cd) {
  60         memcpy(config.data, cd->config.data, sizeof(config.data));
  61         memcpy(BARSize, cd->BARSize, sizeof(BARSize));
  62         memcpy(BARAddrs, cd->BARAddrs, sizeof(BARAddrs));
  63     } else
  64         panic("NULL pointer to configuration data");
  65
  66     // Setup pointer in config space to point to this entry
  67     if (cf->deviceExists(dev,func))
  68         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  69     else
  70         cf->registerDevice(dev, func, this);
  71 }
  72
  73 void
  74 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  75 {
  76     switch(size) {
  77       case sizeof(uint32_t):
  78         memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
  79         *(uint32_t*)data = htoa(*(uint32_t*)data);
  80         DPRINTF(PCIDEV,
  81                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  82                 deviceNum, functionNum, offset, size,
  83                 *(uint32_t*)(config.data + offset));
  84         break;
  85
  86       case sizeof(uint16_t):
  87         memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
  88         *(uint16_t*)data = htoa(*(uint16_t*)data);
  89         DPRINTF(PCIDEV,
  90                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  91                 deviceNum, functionNum, offset, size,
  92                 *(uint16_t*)(config.data + offset));
  93         break;
  94
  95       case sizeof(uint8_t):
  96         memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  97         DPRINTF(PCIDEV,
  98                 "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
  99                 deviceNum, functionNum, offset, size,
 100                 (uint16_t)(*(uint8_t*)(config.data + offset)));
 101         break;
 102
 103       default:
 104         panic("Invalid Read Size");
 105     }
 106 }
 107
 108 void
 109 PciDev::WriteConfig(int offset, int size, uint32_t data)
 110 {
 111     uint32_t barnum;
 112
 113     union {
 114         uint8_t byte_value;
 115         uint16_t half_value;
 116         uint32_t word_value;
 117     };
 118     word_value = data;
 119
 120     DPRINTF(PCIDEV,
 121             "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
 122             deviceNum, functionNum, offset, size, word_value);
 123
 124     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 125
 126     switch (size) {
 127       case sizeof(uint8_t): // 1-byte access
 128         switch (offset) {
 129           case PCI0_INTERRUPT_LINE:
 130           case PCI_CACHE_LINE_SIZE:
 131           case PCI_LATENCY_TIMER:
 132             *(uint8_t *)&config.data[offset] = htoa(byte_value);
 133             break;
 134
 135           default:
 136             panic("writing to a read only register");
 137         }
 138         break;
 139
 140       case sizeof(uint16_t): // 2-byte access
 141         switch (offset) {
 142           case PCI_COMMAND:
 143           case PCI_STATUS:
 144           case PCI_CACHE_LINE_SIZE:
 145             *(uint16_t *)&config.data[offset] = htoa(half_value);
 146             break;
 147
 148           default:
 149             panic("writing to a read only register");
 150         }
 151         break;
 152
 153       case sizeof(uint16_t)+1: // 3-byte access
 154         panic("invalid access size");
 155
 156       case sizeof(uint32_t): // 4-byte access
 157         switch (offset) {
 158           case PCI0_BASE_ADDR0:
 159           case PCI0_BASE_ADDR1:
 160           case PCI0_BASE_ADDR2:
 161           case PCI0_BASE_ADDR3:
 162           case PCI0_BASE_ADDR4:
 163           case PCI0_BASE_ADDR5:
 164             // Writing 0xffffffff to a BAR tells the card to set the
 165             // value of the bar
 166             // to size of memory it needs
 167             if (word_value == 0xffffffff) {
 168                 // This is I/O Space, bottom two bits are read only
 169                 if (htoa(config.data[offset]) & 0x1) {
 170                     *(uint32_t *)&config.data[offset] = htoa(
 171                         ~(BARSize[barnum] - 1) |
 172                         (htoa(config.data[offset]) & 0x3));
 173                 } else {
 174                     // This is memory space, bottom four bits are read only
 175                     *(uint32_t *)&config.data[offset] = htoa(
 176                         ~(BARSize[barnum] - 1) |
 177                         (htoa(config.data[offset]) & 0xF));
 178                 }
 179             } else {
 180                 // This is I/O Space, bottom two bits are read only
 181                 if(htoa(config.data[offset]) & 0x1) {
 182                     *(uint32_t *)&config.data[offset] = htoa((word_value & ~0x3) |
 183                         (htoa(config.data[offset]) & 0x3));
 184
 185                     if (word_value & ~0x1) {
 186                         Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
 187                         Addr base_size = BARSize[barnum];
 188
 189                         // It's never been set
 190                         if (BARAddrs[barnum] == 0)
 191                             mmu->add_child((FunctionalMemory *)this,
 192                                            RangeSize(base_addr, base_size));
 193                         else
 194                             mmu->update_child((FunctionalMemory *)this,
 195                                               RangeSize(BARAddrs[barnum],
 196                                                         base_size),
 197                                               RangeSize(base_addr, base_size));
 198
 199                         BARAddrs[barnum] = base_addr;
 200                     }
 201
 202                 } else {
 203                     // This is memory space, bottom four bits are read only
 204                     *(uint32_t *)&config.data[offset] = htoa((word_value & ~0xF) |
 205                         (htoa(config.data[offset]) & 0xF));
 206
 207                     if (word_value & ~0x3) {
 208                         Addr base_addr = (word_value & ~0x3) +
 209                             TSUNAMI_PCI0_MEMORY;
 210
 211                         Addr base_size = BARSize[barnum];
 212
 213                         // It's never been set
 214                         if (BARAddrs[barnum] == 0)
 215                             mmu->add_child((FunctionalMemory *)this,
 216                                            RangeSize(base_addr, base_size));
 217                         else
 218                             mmu->update_child((FunctionalMemory *)this,
 219                                               RangeSize(BARAddrs[barnum],
 220                                                         base_size),
 221                                               RangeSize(base_addr, base_size));
 222
 223                         BARAddrs[barnum] = base_addr;
 224                     }
 225                  }
 226             }
 227             break;
 228
 229           case PCI0_ROM_BASE_ADDR:
 230             if (word_value == 0xfffffffe)
 231                 *(uint32_t *)&config.data[offset] = 0xffffffff;
 232             else
 233                 *(uint32_t *)&config.data[offset] = htoa(word_value);
 234             break;
 235
 236           case PCI_COMMAND:
 237             // This could also clear some of the error bits in the Status
 238             // register. However they should never get set, so lets ignore
 239             // it for now
 240             *(uint16_t *)&config.data[offset] = htoa(half_value);
 241             break;
 242
 243           default:
 244             DPRINTF(PCIDEV, "Writing to a read only register");
 245         }
 246         break;
 247     }
 248 }
 249
 250 void
 251 PciDev::serialize(ostream &os)
 252 {
 253     SERIALIZE_ARRAY(BARSize, 6);
 254     SERIALIZE_ARRAY(BARAddrs, 6);
 255     SERIALIZE_ARRAY(config.data, 64);
 256 }
 257
 258 void
 259 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 260 {
 261     UNSERIALIZE_ARRAY(BARSize, 6);
 262     UNSERIALIZE_ARRAY(BARAddrs, 6);
 263     UNSERIALIZE_ARRAY(config.data, 64);
 264
 265     // Add the MMU mappings for the BARs
 266     for (int i=0; i < 6; i++) {
 267         if (BARAddrs[i] != 0)
 268             mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
 269     }
 270 }
 271
 272 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 273
 274 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 275
 276     Param<uint16_t> VendorID;
 277     Param<uint16_t> DeviceID;
 278     Param<uint16_t> Command;
 279     Param<uint16_t> Status;
 280     Param<uint8_t> Revision;
 281     Param<uint8_t> ProgIF;
 282     Param<uint8_t> SubClassCode;
 283     Param<uint8_t> ClassCode;
 284     Param<uint8_t> CacheLineSize;
 285     Param<uint8_t> LatencyTimer;
 286     Param<uint8_t> HeaderType;
 287     Param<uint8_t> BIST;
 288     Param<uint32_t> BAR0;
 289     Param<uint32_t> BAR1;
 290     Param<uint32_t> BAR2;
 291     Param<uint32_t> BAR3;
 292     Param<uint32_t> BAR4;
 293     Param<uint32_t> BAR5;
 294     Param<uint32_t> CardbusCIS;
 295     Param<uint16_t> SubsystemVendorID;
 296     Param<uint16_t> SubsystemID;
 297     Param<uint32_t> ExpansionROM;
 298     Param<uint8_t> InterruptLine;
 299     Param<uint8_t> InterruptPin;
 300     Param<uint8_t> MinimumGrant;
 301     Param<uint8_t> MaximumLatency;
 302     Param<uint32_t> BAR0Size;
 303     Param<uint32_t> BAR1Size;
 304     Param<uint32_t> BAR2Size;
 305     Param<uint32_t> BAR3Size;
 306     Param<uint32_t> BAR4Size;
 307     Param<uint32_t> BAR5Size;
 308
 309 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 310
 311 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 312
 313     INIT_PARAM(VendorID, "Vendor ID"),
 314     INIT_PARAM(DeviceID, "Device ID"),
 315     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 316     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 317     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 318     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 319     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 320     INIT_PARAM(ClassCode, "Class Code"),
 321     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 322     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 323     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 324     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 325     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 326     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 327     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 328     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 329     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 330     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 331     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 332     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 333     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 334     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 335     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 336     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 337     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 338     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 339     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 340     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 341     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 342     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 343     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 344     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 345
 346 END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 347
 348 CREATE_SIM_OBJECT(PciConfigData)
 349 {
 350     PciConfigData *data = new PciConfigData(getInstanceName());
 351
 352     data->config.hdr.vendor = htoa(VendorID);
 353     data->config.hdr.device = htoa(DeviceID);
 354     data->config.hdr.command = htoa(Command);
 355     data->config.hdr.status = htoa(Status);
 356     data->config.hdr.revision = htoa(Revision);
 357     data->config.hdr.progIF = htoa(ProgIF);
 358     data->config.hdr.subClassCode = htoa(SubClassCode);
 359     data->config.hdr.classCode = htoa(ClassCode);
 360     data->config.hdr.cacheLineSize = htoa(CacheLineSize);
 361     data->config.hdr.latencyTimer = htoa(LatencyTimer);
 362     data->config.hdr.headerType = htoa(HeaderType);
 363     data->config.hdr.bist = htoa(BIST);
 364
 365     data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
 366     data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
 367     data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
 368     data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
 369     data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
 370     data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
 371     data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
 372     data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
 373     data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
 374     data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
 375     data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
 376     data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
 377     data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
 378     data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
 379
 380     data->BARSize[0] = BAR0Size;
 381     data->BARSize[1] = BAR1Size;
 382     data->BARSize[2] = BAR2Size;
 383     data->BARSize[3] = BAR3Size;
 384     data->BARSize[4] = BAR4Size;
 385     data->BARSize[5] = BAR5Size;
 386
 387     return data;
 388 }
 389
 390 REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
 391
 392 #endif // DOXYGEN_SHOULD_SKIP_THIS