dev/pcidev.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * A single PCI device configuration space entry.
  31  */
  32
  33 #include <list>
  34 #include <sstream>
  35 #include <string>
  36 #include <vector>
  37
  38 #include "base/inifile.hh"
  39 #include "base/misc.hh"
  40 #include "base/str.hh"  // for to_number
  41 #include "base/trace.hh"
  42 #include "dev/pciareg.h"
  43 #include "dev/scsi_ctrl.hh"
  44 #include "dev/pcidev.hh"
  45 #include "dev/pciconfigall.hh"
  46 #include "mem/functional_mem/memory_control.hh"
  47 #include "sim/builder.hh"
  48 #include "sim/param.hh"
  49 #include "sim/universe.hh"
  50
  51 using namespace std;
  52
  53 PciDev::PciDev(const string &name, PCIConfigAll *cf, uint32_t bus,
  54                uint32_t dev, uint32_t func)
  55     : MMapDevice(name), ConfigSpace(cf), Bus(bus), Device(dev), Function(func), MMU(mmu)
  56 {
  57     memset(config.data, 0, sizeof(config.data));
  58     memset(BARAddrs, 0, sizeof(Addr) * 6);
  59
  60     // Setup pointer in config space to point to this entry
  61     if(cf->devices[dev][func] != NULL)
  62         panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
  63     else
  64         cf->devices[dev][func] = this;
  65 }
  66
  67
  68 void
  69 PciDev::ReadConfig(int offset, int size, uint8_t *data)
  70 {
  71     switch(size) {
  72         case sizeof(uint32_t):
  73             memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
  74             DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
  75                 Device, Function, offset, *(uint32_t*)(config.data + offset));
  76             break;
  77         case sizeof(uint16_t):
  78             memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
  79             DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
  80                 Device, Function, offset, *(uint16_t*)(config.data + offset));
  81             break;
  82         case sizeof(uint8_t):
  83             memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
  84             printf("data: %#x\n", *(uint8_t*)(config.data + offset));
  85             DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
  86                 Device, Function, offset, *(uint8_t*)(config.data + offset));
  87             break;
  88         default:
  89             panic("Invalid Read Size");
  90     }
  91 }
  92
  93
  94 void
  95 PciDev::WriteConfig(int offset, int size, uint32_t data)
  96 {
  97     uint32_t barnum;
  98
  99     union {
 100         uint8_t byte_value;
 101         uint16_t half_value;
 102         uint32_t word_value;
 103     };
 104     word_value = data;
 105
 106     DPRINTF(PCIDEV, "write device: %#x function: %#x register: %#x size: %#x data: %#x\n",
 107                 Device, Function, offset, size, word_value);
 108
 109     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 110
 111     switch (size) {
 112       case sizeof(uint8_t): // 1-byte access
 113         switch (offset) {
 114           case PCI0_INTERRUPT_LINE:
 115           case PCI_CACHE_LINE_SIZE:
 116             *(uint8_t *)&config.data[offset] = byte_value;
 117             break;
 118
 119           default:
 120             panic("writing to a read only register");
 121         }
 122         break;
 123
 124       case sizeof(uint16_t): // 2-byte access
 125         switch (offset) {
 126           case PCI_COMMAND:
 127           case PCI_STATUS:
 128           case PCI_CACHE_LINE_SIZE:
 129             *(uint16_t *)&config.data[offset] = half_value;
 130             break;
 131
 132           default:
 133             panic("writing to a read only register");
 134         }
 135         break;
 136
 137       case sizeof(uint16_t)+1: // 3-byte access
 138         panic("invalid access size");
 139
 140       case sizeof(uint32_t): // 4-byte access
 141         switch (offset) {
 142           case PCI0_BASE_ADDR0:
 143           case PCI0_BASE_ADDR1:
 144           case PCI0_BASE_ADDR2:
 145           case PCI0_BASE_ADDR3:
 146           case PCI0_BASE_ADDR4:
 147           case PCI0_BASE_ADDR5:
 148               // Writing 0xffffffff to a BAR tells the card to set the value of the bar
 149               // to size of memory it needs
 150               if (word_value == 0xffffffff) {
 151                  // This is I/O Space, bottom two bits are read only
 152                   if(config.data[offset] & 0x1) {
 153                     *(uint32_t *)&config.data[offset] =
 154                         ~(BARSize[barnum] - 1) |
 155                         (config.data[offset] & 0x3);
 156                   } else {
 157                   // This is memory space, bottom four bits are read only
 158                     *(uint32_t *)&config.data[offset] =
 159                         ~(BARSize[barnum] - 1) |
 160                         (config.data[offset] & 0xF);
 161                   }
 162
 163
 164               } else {
 165                   // This is I/O Space, bottom two bits are read only
 166                   if(config.data[offset] & 0x1) {
 167                     *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
 168                                                         (config.data[offset] & 0x3);
 169                     if (word_value) {
 170                         // It's never been set
 171                         if (BARAddr[barnum] == 0)
 172                             AddMapping(word_value, BARSize[barnum]-1, MMU);
 173                         else
 174                             UpdateMapping(BARAddr[barnum], BARSize[barnum]-1,
 175                                           word_value, BARSize[barnum]-1, MMU);
 176                         BARAddr[barnum] = word_value;
 177                     }
 178
 179                   } else {
 180                   // This is memory space, bottom four bits are read only
 181                     *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
 182                                                         (config.data[offset] & 0xF);
 183                   }
 184               }
 185             break;
 186           case PCI0_ROM_BASE_ADDR:
 187                     if (word_value == 0xfffffffe)
 188                         *(uint32_t *)&config.data[offset] = 0xffffffff;
 189                     else
 190                         *(uint32_t *)&config.data[offset] = word_value;
 191                 break;
 192           case PCI_COMMAND:
 193                 // This could also clear some of the error bits in the Status register
 194                 // However they should never get set, so lets ignore it for now
 195                 *(uint16_t *)&config.data[offset] = half_value;
 196                 break;
 197
 198
 199           default:
 200             panic("writing to a read only register");
 201         }
 202         break;
 203     }
 204
 205 }
 206
 207 void
 208 PciDev::serialize(ostream &os)
 209 {
 210     SERIALIZE_ARRAY(config.data, 64);
 211 }
 212
 213 void
 214 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 215 {
 216     UNSERIALIZE_ARRAY(config.data, 64);
 217 }
 218
 219
 220 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev)
 221
 222     Param<int> VendorID;
 223     Param<int> DeviceID;
 224     Param<int> Command;
 225     Param<int> Status;
 226     Param<int> Revision;
 227     Param<int> ProgIF;
 228     Param<int> SubClassCode;
 229     Param<int> ClassCode;
 230     Param<int> CacheLineSize;
 231     Param<int> LatencyTimer;
 232     Param<int> HeaderType;
 233     Param<int> BIST;
 234     Param<uint32_t> BAR0;
 235     Param<uint32_t> BAR1;
 236     Param<uint32_t> BAR2;
 237     Param<uint32_t> BAR3;
 238     Param<uint32_t> BAR4;
 239     Param<uint32_t> BAR5;
 240     Param<uint32_t> CardbusCIS;
 241     Param<int> SubsystemVendorID;
 242     Param<int> SubsystemID;
 243     Param<uint32_t> ExpansionROM;
 244     Param<int> InterruptLine;
 245     Param<int> InterruptPin;
 246     Param<int> MinimumGrant;
 247     Param<int> MaximumLatency;
 248     Param<uint32_t> BAR0Size;
 249     Param<uint32_t> BAR1Size;
 250     Param<uint32_t> BAR2Size;
 251     Param<uint32_t> BAR3Size;
 252     Param<uint32_t> BAR4Size;
 253     Param<uint32_t> BAR5Size;
 254
 255     SimObjectParam<MemoryController *> mmu;
 256     SimObjectParam<PCIConfigAll*> cf;
 257     Param<Addr> addr;
 258     Param<Addr> mask;
 259     Param<uint32_t> bus;
 260     Param<uint32_t> device;
 261     Param<uint32_t> func;
 262
 263
 264 END_DECLARE_SIM_OBJECT_PARAMS(PciDev)
 265
 266 BEGIN_INIT_SIM_OBJECT_PARAMS(PciDev)
 267
 268     INIT_PARAM(VendorID, "Vendor ID"),
 269     INIT_PARAM(DeviceID, "Device ID"),
 270     INIT_PARAM_DFLT(Command, "Command Register", 0x00),
 271     INIT_PARAM_DFLT(Status, "Status Register", 0x00),
 272     INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
 273     INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
 274     INIT_PARAM(SubClassCode, "Sub-Class Code"),
 275     INIT_PARAM(ClassCode, "Class Code"),
 276     INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
 277     INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
 278     INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
 279     INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
 280     INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
 281     INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
 282     INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
 283     INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
 284     INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
 285     INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
 286     INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
 287     INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
 288     INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
 289     INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
 290     INIT_PARAM(InterruptLine, "Interrupt Line Register"),
 291     INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
 292     INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
 293     INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
 294     INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
 295     INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
 296     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
 297     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
 298     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
 299     INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00),
 300
 301     INIT_PARAM(cf, "Pointer to Configspace device"),
 302     INIT_PARAM(bus, "PCI Bus Number"),
 303     INIT_PARAM(device, "PCI Device number"),
 304     INIT_PARAM(func, "PCI Function Number")
 305
 306
 307 END_INIT_SIM_OBJECT_PARAMS(PciDev)
 308
 309 CREATE_SIM_OBJECT(PciDev)
 310 {
 311     PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func);
 312
 313     dev->config.hdr.vendor = VendorID;
 314     dev->config.hdr.device = DeviceID;
 315     dev->config.hdr.command = Command;
 316     dev->config.hdr.status = Status;
 317     dev->config.hdr.revision = Revision;
 318     dev->config.hdr.progIF = ProgIF;
 319     dev->config.hdr.subClassCode = SubClassCode;
 320     dev->config.hdr.classCode = ClassCode;
 321     dev->config.hdr.cacheLineSize = CacheLineSize;
 322     dev->config.hdr.latencyTimer = LatencyTimer;
 323     dev->config.hdr.headerType = HeaderType;
 324     dev->config.hdr.bist = BIST;
 325
 326     dev->config.hdr.pci0.baseAddr0 = BAR0;
 327     dev->config.hdr.pci0.baseAddr1 = BAR1;
 328     dev->config.hdr.pci0.baseAddr2 = BAR2;
 329     dev->config.hdr.pci0.baseAddr3 = BAR3;
 330     dev->config.hdr.pci0.baseAddr4 = BAR4;
 331     dev->config.hdr.pci0.baseAddr5 = BAR5;
 332     dev->config.hdr.pci0.cardbusCIS = CardbusCIS;
 333     dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
 334     dev->config.hdr.pci0.subsystemID = SubsystemVendorID;
 335     dev->config.hdr.pci0.expansionROM = ExpansionROM;
 336     dev->config.hdr.pci0.interruptLine = InterruptLine;
 337     dev->config.hdr.pci0.interruptPin = InterruptPin;
 338     dev->config.hdr.pci0.minimumGrant = MinimumGrant;
 339     dev->config.hdr.pci0.maximumLatency = MaximumLatency;
 340
 341     dev->BARSize[0] = BAR0Size;
 342     dev->BARSize[1] = BAR1Size;
 343     dev->BARSize[2] = BAR2Size;
 344     dev->BARSize[3] = BAR3Size;
 345     dev->BARSize[4] = BAR4Size;
 346     dev->BARSize[5] = BAR5Size;
 347
 348     return dev;
 349 }
 350
 351 REGISTER_SIM_OBJECT("PciDev", PciDev)