dev/pcireg.h

   1 /*
   2  * Copyright (c) 2001-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /* @file
  30  * Device register definitions for a device's PCI config space
  31  */
  32
  33 #ifndef __PCIREG_H__
  34 #define __PCIREG_H__
  35
  36 #include <sys/types.h>
  37
  38 union PCIConfig {
  39     uint8_t     data[64];
  40
  41     struct hdr {
  42         uint16_t        vendor;
  43         uint16_t        device;
  44         uint16_t        command;
  45         uint16_t        status;
  46         uint8_t         revision;
  47         uint8_t         progIF;
  48         uint8_t         subClassCode;
  49         uint8_t         classCode;
  50         uint8_t         cacheLineSize;
  51         uint8_t         latencyTimer;
  52         uint8_t         headerType;
  53         uint8_t         bist;
  54
  55         union {
  56             struct {
  57                 uint32_t        baseAddr0;
  58                 uint32_t        baseAddr1;
  59                 uint32_t        baseAddr2;
  60                 uint32_t        baseAddr3;
  61                 uint32_t        baseAddr4;
  62                 uint32_t        baseAddr5;
  63                 uint32_t        cardbusCIS;
  64                 uint16_t        subsystemVendorID;
  65                 uint16_t        subsystemID;
  66                 uint32_t        expansionROM;
  67                 uint32_t        reserved0;
  68                 uint32_t        reserved1;
  69                 uint8_t         interruptLine;
  70                 uint8_t         interruptPin;
  71                 uint8_t         minimumGrant;
  72                 uint8_t         maximumLatency;
  73             } pci0;
  74
  75             struct {
  76                 uint32_t        baseAddr0;
  77                 uint32_t        baseAddr1;
  78                 uint8_t         priBusNum;
  79                 uint8_t         secBusNum;
  80                 uint8_t         subBusNum;
  81                 uint8_t         secLatency;
  82                 uint8_t         ioBase;
  83                 uint8_t         minimumGrantioLimit;
  84                 uint16_t        secStatus;
  85                 uint16_t        memBase;
  86                 uint16_t        memLimit;
  87                 uint16_t        prefetchMemBase;
  88                 uint16_t        prefetchMemLimit;
  89                 uint32_t        prfBaseUpper32;
  90                 uint32_t        prfLimitUpper32;
  91                 uint16_t        ioBaseUpper16;
  92                 uint16_t        ioLimitUpper16;
  93                 uint32_t        reserved0;
  94                 uint32_t        expansionROM;
  95                 uint8_t         interruptLine;
  96                 uint8_t         interruptPin;
  97                 uint16_t        bridgeControl;
  98             } pci1;
  99         };
 100     } hdr;
 101 };
 102
 103 // Common PCI offsets
 104 #define PCI_VENDOR_ID           0x00    // Vendor ID                    ro
 105 #define PCI_DEVICE_ID           0x02    // Device ID                    ro
 106 #define PCI_COMMAND             0x04    // Command                      rw
 107 #define PCI_STATUS              0x06    // Status                       rw
 108 #define PCI_REVISION_ID         0x08    // Revision ID                  ro
 109 #define PCI_CLASS_CODE          0x09    // Class Code                   ro
 110 #define PCI_SUB_CLASS_CODE      0x0A    // Sub Class Code               ro
 111 #define PCI_BASE_CLASS_CODE     0x0B    // Base Class Code              ro
 112 #define PCI_CACHE_LINE_SIZE     0x0C    // Cache Line Size              ro+
 113 #define PCI_LATENCY_TIMER       0x0D    // Latency Timer                ro+
 114 #define PCI_HEADER_TYPE         0x0E    // Header Type                  ro
 115 #define PCI_BIST                0x0F    // Built in self test           rw
 116
 117 // some pci command reg bitfields
 118 #define PCI_CMD_BME     0x04 // Bus master function enable
 119 #define PCI_CMD_MSE     0x02 // Memory Space Access enable
 120 #define PCI_CMD_IOSE    0x01 // I/O space enable
 121
 122 // Type 0 PCI offsets
 123 #define PCI0_BASE_ADDR0         0x10    // Base Address 0               rw
 124 #define PCI0_BASE_ADDR1         0x14    // Base Address 1               rw
 125 #define PCI0_BASE_ADDR2         0x18    // Base Address 2               rw
 126 #define PCI0_BASE_ADDR3         0x1C    // Base Address 3               rw
 127 #define PCI0_BASE_ADDR4         0x20    // Base Address 4               rw
 128 #define PCI0_BASE_ADDR5         0x24    // Base Address 5               rw
 129 #define PCI0_CIS                0x28    // CardBus CIS Pointer          ro
 130 #define PCI0_SUB_VENDOR_ID      0x2C    // Sub-Vendor ID                ro
 131 #define PCI0_SUB_SYSTEM_ID      0x2E    // Sub-System ID                ro
 132 #define PCI0_ROM_BASE_ADDR      0x30    // Expansion ROM Base Address   rw
 133 #define PCI0_RESERVED0          0x34
 134 #define PCI0_RESERVED1          0x38
 135 #define PCI0_INTERRUPT_LINE     0x3C    // Interrupt Line               rw
 136 #define PCI0_INTERRUPT_PIN      0x3D    // Interrupt Pin                ro
 137 #define PCI0_MINIMUM_GRANT      0x3E    // Maximum Grant                ro
 138 #define PCI0_MAXIMUM_LATENCY    0x3F    // Maximum Latency              ro
 139
 140 // Type 1 PCI offsets
 141 #define PCI1_BASE_ADDR0         0x10    // Base Address 0               rw
 142 #define PCI1_BASE_ADDR1         0x14    // Base Address 1               rw
 143 #define PCI1_PRI_BUS_NUM        0x18    // Primary Bus Number           rw
 144 #define PCI1_SEC_BUS_NUM        0x19    // Secondary Bus Number         rw
 145 #define PCI1_SUB_BUS_NUM        0x1A    // Subordinate Bus Number       rw
 146 #define PCI1_SEC_LAT_TIMER      0x1B    // Secondary Latency Timer      ro+
 147 #define PCI1_IO_BASE            0x1C    // I/O Base                     rw
 148 #define PCI1_IO_LIMIT           0x1D    // I/O Limit                    rw
 149 #define PCI1_SECONDARY_STATUS   0x1E    // Secondary Status             rw
 150 #define PCI1_MEM_BASE           0x20    // Memory Base                  rw
 151 #define PCI1_MEM_LIMIT          0x22    // Memory Limit                 rw
 152 #define PCI1_PRF_MEM_BASE       0x24    // Prefetchable Memory Base     rw
 153 #define PCI1_PRF_MEM_LIMIT      0x26    // Prefetchable Memory Limit    rw
 154 #define PCI1_PRF_BASE_UPPER     0x28    // Prefetchable Base Upper 32   rw
 155 #define PCI1_PRF_LIMIT_UPPER    0x2C    // Prefetchable Limit Upper 32  rw
 156 #define PCI1_IO_BASE_UPPER      0x30    // I/O Base Upper 16 bits       rw
 157 #define PCI1_IO_LIMIT_UPPER     0x32    // I/O Limit Upper 16 bits      rw
 158 #define PCI1_RESERVED           0x34    // Reserved                     ro
 159 #define PCI1_ROM_BASE_ADDR      0x38    // Expansion ROM Base Address   rw
 160 #define PCI1_INTR_LINE          0x3C    // Interrupt Line               rw
 161 #define PCI1_INTR_PIN           0x3D    // Interrupt Pin                ro
 162 #define PCI1_BRIDGE_CTRL        0x3E    // Bridge Control               rw
 163
 164 // Device specific offsets
 165 #define PCI_DEVICE_SPECIFIC             0x40    // 192 bytes
 166
 167 // Some Vendor IDs
 168 #define PCI_VENDOR_DEC                  0x1011
 169 #define PCI_VENDOR_NCR                  0x101A
 170 #define PCI_VENDOR_QLOGIC               0x1077
 171 #define PCI_VENDOR_SIMOS                0x1291
 172
 173 // Some Product IDs
 174 #define PCI_PRODUCT_DEC_PZA             0x0008
 175 #define PCI_PRODUCT_NCR_810             0x0001
 176 #define PCI_PRODUCT_QLOGIC_ISP1020      0x1020
 177 #define PCI_PRODUCT_SIMOS_SIMOS         0x1291
 178 #define PCI_PRODUCT_SIMOS_ETHER         0x1292
 179
 180 #endif // __PCIREG_H__