dev/sinic.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cstdio>
  30 #include <deque>
  31 #include <string>
  32
  33 #include "base/inet.hh"
  34 #include "cpu/exec_context.hh"
  35 #include "cpu/intr_control.hh"
  36 #include "dev/etherlink.hh"
  37 #include "dev/sinic.hh"
  38 #include "dev/pciconfigall.hh"
  39 #include "mem/bus/bus.hh"
  40 #include "mem/bus/dma_interface.hh"
  41 #include "mem/bus/pio_interface.hh"
  42 #include "mem/bus/pio_interface_impl.hh"
  43 #include "mem/functional/memory_control.hh"
  44 #include "mem/functional/physical.hh"
  45 #include "sim/builder.hh"
  46 #include "sim/debug.hh"
  47 #include "sim/eventq.hh"
  48 #include "sim/host.hh"
  49 #include "sim/stats.hh"
  50 #include "targetarch/vtophys.hh"
  51
  52 using namespace Net;
  53
  54 namespace Sinic {
  55
  56 const char *RxStateStrings[] =
  57 {
  58     "rxIdle",
  59     "rxFifoBlock",
  60     "rxBeginCopy",
  61     "rxCopy",
  62     "rxCopyDone"
  63 };
  64
  65 const char *TxStateStrings[] =
  66 {
  67     "txIdle",
  68     "txFifoBlock",
  69     "txBeginCopy",
  70     "txCopy",
  71     "txCopyDone"
  72 };
  73
  74
  75 ///////////////////////////////////////////////////////////////////////
  76 //
  77 // Sinic PCI Device
  78 //
  79 Base::Base(Params *p)
  80     : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
  81       intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
  82       cpuPendingIntr(false), intrEvent(0), interface(NULL)
  83 {
  84 }
  85
  86 Device::Device(Params *p)
  87     : Base(p), plat(p->plat), physmem(p->physmem),
  88       rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
  89       rxKickTick(0), txKickTick(0),
  90       txEvent(this), rxDmaEvent(this), txDmaEvent(this),
  91       dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
  92       dmaWriteDelay(p->dma_write_delay), dmaWriteFactor(p->dma_write_factor)
  93 {
  94     reset();
  95
  96     if (p->io_bus) {
  97         pioInterface = newPioInterface(p->name + ".pio", p->hier, p->io_bus,
  98                                        this, &Device::cacheAccess);
  99
 100         pioLatency = p->pio_latency * p->io_bus->clockRate;
 101
 102         if (p->payload_bus)
 103             dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
 104                                                  p->payload_bus, 1,
 105                                                  p->dma_no_allocate);
 106         else
 107             dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
 108                                                  p->io_bus, 1,
 109                                                  p->dma_no_allocate);
 110     } else if (p->payload_bus) {
 111         pioInterface = newPioInterface(p->name + ".pio", p->hier,
 112                                        p->payload_bus, this,
 113                                        &Device::cacheAccess);
 114
 115         pioLatency = p->pio_latency * p->payload_bus->clockRate;
 116
 117         dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
 118                                              p->payload_bus, 1,
 119                                              p->dma_no_allocate);
 120     }
 121 }
 122
 123 Device::~Device()
 124 {}
 125
 126 void
 127 Device::regStats()
 128 {
 129     rxBytes
 130         .name(name() + ".rxBytes")
 131         .desc("Bytes Received")
 132         .prereq(rxBytes)
 133         ;
 134
 135     rxBandwidth
 136         .name(name() + ".rxBandwidth")
 137         .desc("Receive Bandwidth (bits/s)")
 138         .precision(0)
 139         .prereq(rxBytes)
 140         ;
 141
 142     rxPackets
 143         .name(name() + ".rxPackets")
 144         .desc("Number of Packets Received")
 145         .prereq(rxBytes)
 146         ;
 147
 148     rxPacketRate
 149         .name(name() + ".rxPPS")
 150         .desc("Packet Reception Rate (packets/s)")
 151         .precision(0)
 152         .prereq(rxBytes)
 153         ;
 154
 155     rxIpPackets
 156         .name(name() + ".rxIpPackets")
 157         .desc("Number of IP Packets Received")
 158         .prereq(rxBytes)
 159         ;
 160
 161     rxTcpPackets
 162         .name(name() + ".rxTcpPackets")
 163         .desc("Number of Packets Received")
 164         .prereq(rxBytes)
 165         ;
 166
 167     rxUdpPackets
 168         .name(name() + ".rxUdpPackets")
 169         .desc("Number of UDP Packets Received")
 170         .prereq(rxBytes)
 171         ;
 172
 173     rxIpChecksums
 174         .name(name() + ".rxIpChecksums")
 175         .desc("Number of rx IP Checksums done by device")
 176         .precision(0)
 177         .prereq(rxBytes)
 178         ;
 179
 180     rxTcpChecksums
 181         .name(name() + ".rxTcpChecksums")
 182         .desc("Number of rx TCP Checksums done by device")
 183         .precision(0)
 184         .prereq(rxBytes)
 185         ;
 186
 187     rxUdpChecksums
 188         .name(name() + ".rxUdpChecksums")
 189         .desc("Number of rx UDP Checksums done by device")
 190         .precision(0)
 191         .prereq(rxBytes)
 192         ;
 193
 194     totBandwidth
 195         .name(name() + ".totBandwidth")
 196         .desc("Total Bandwidth (bits/s)")
 197         .precision(0)
 198         .prereq(totBytes)
 199         ;
 200
 201     totPackets
 202         .name(name() + ".totPackets")
 203         .desc("Total Packets")
 204         .precision(0)
 205         .prereq(totBytes)
 206         ;
 207
 208     totBytes
 209         .name(name() + ".totBytes")
 210         .desc("Total Bytes")
 211         .precision(0)
 212         .prereq(totBytes)
 213         ;
 214
 215     totPacketRate
 216         .name(name() + ".totPPS")
 217         .desc("Total Tranmission Rate (packets/s)")
 218         .precision(0)
 219         .prereq(totBytes)
 220         ;
 221
 222     txBytes
 223         .name(name() + ".txBytes")
 224         .desc("Bytes Transmitted")
 225         .prereq(txBytes)
 226         ;
 227
 228     txBandwidth
 229         .name(name() + ".txBandwidth")
 230         .desc("Transmit Bandwidth (bits/s)")
 231         .precision(0)
 232         .prereq(txBytes)
 233         ;
 234
 235     txPackets
 236         .name(name() + ".txPackets")
 237         .desc("Number of Packets Transmitted")
 238         .prereq(txBytes)
 239         ;
 240
 241     txPacketRate
 242         .name(name() + ".txPPS")
 243         .desc("Packet Tranmission Rate (packets/s)")
 244         .precision(0)
 245         .prereq(txBytes)
 246         ;
 247
 248     txIpPackets
 249         .name(name() + ".txIpPackets")
 250         .desc("Number of IP Packets Transmitted")
 251         .prereq(txBytes)
 252         ;
 253
 254     txTcpPackets
 255         .name(name() + ".txTcpPackets")
 256         .desc("Number of TCP Packets Transmitted")
 257         .prereq(txBytes)
 258         ;
 259
 260     txUdpPackets
 261         .name(name() + ".txUdpPackets")
 262         .desc("Number of Packets Transmitted")
 263         .prereq(txBytes)
 264         ;
 265
 266     txIpChecksums
 267         .name(name() + ".txIpChecksums")
 268         .desc("Number of tx IP Checksums done by device")
 269         .precision(0)
 270         .prereq(txBytes)
 271         ;
 272
 273     txTcpChecksums
 274         .name(name() + ".txTcpChecksums")
 275         .desc("Number of tx TCP Checksums done by device")
 276         .precision(0)
 277         .prereq(txBytes)
 278         ;
 279
 280     txUdpChecksums
 281         .name(name() + ".txUdpChecksums")
 282         .desc("Number of tx UDP Checksums done by device")
 283         .precision(0)
 284         .prereq(txBytes)
 285         ;
 286
 287     txBandwidth = txBytes * Stats::constant(8) / simSeconds;
 288     rxBandwidth = rxBytes * Stats::constant(8) / simSeconds;
 289     totBandwidth = txBandwidth + rxBandwidth;
 290     totBytes = txBytes + rxBytes;
 291     totPackets = txPackets + rxPackets;
 292     txPacketRate = txPackets / simSeconds;
 293     rxPacketRate = rxPackets / simSeconds;
 294 }
 295
 296 /**
 297  * This is to write to the PCI general configuration registers
 298  */
 299 void
 300 Device::writeConfig(int offset, int size, const uint8_t *data)
 301 {
 302     switch (offset) {
 303       case PCI0_BASE_ADDR0:
 304         // Need to catch writes to BARs to update the PIO interface
 305         PciDev::writeConfig(offset, size, data);
 306         if (BARAddrs[0] != 0) {
 307             if (pioInterface)
 308                 pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
 309
 310             BARAddrs[0] &= EV5::PAddrUncachedMask;
 311         }
 312         break;
 313
 314       default:
 315         PciDev::writeConfig(offset, size, data);
 316     }
 317 }
 318
 319 /**
 320  * This reads the device registers, which are detailed in the NS83820
 321  * spec sheet
 322  */
 323 Fault
 324 Device::read(MemReqPtr &req, uint8_t *data)
 325 {
 326     assert(config.command & PCI_CMD_MSE);
 327
 328     //The mask is to give you only the offset into the device register file
 329     Addr daddr = req->paddr & 0xfff;
 330
 331     if (Regs::regSize(daddr) == 0)
 332         panic("invalid address: da=%#x pa=%#x va=%#x size=%d",
 333               daddr, req->paddr, req->vaddr, req->size);
 334
 335     if (req->size != Regs::regSize(daddr))
 336         panic("invalid size for reg %s: da=%#x pa=%#x va=%#x size=%d",
 337               Regs::regName(daddr), daddr, req->paddr, req->vaddr, req->size);
 338
 339     DPRINTF(EthernetPIO, "read reg=%s da=%#x pa=%#x va=%#x size=%d\n",
 340             Regs::regName(daddr), daddr, req->paddr, req->vaddr, req->size);
 341
 342     uint32_t &reg32 = *(uint32_t *)data;
 343     uint64_t &reg64 = *(uint64_t *)data;
 344
 345     switch (daddr) {
 346       case Regs::Config:
 347         reg32 = regs.Config;
 348         break;
 349
 350       case Regs::RxMaxCopy:
 351         reg32 = regs.RxMaxCopy;
 352         break;
 353
 354       case Regs::TxMaxCopy:
 355         reg32 = regs.TxMaxCopy;
 356         break;
 357
 358       case Regs::RxThreshold:
 359         reg32 = regs.RxThreshold;
 360         break;
 361
 362       case Regs::TxThreshold:
 363         reg32 = regs.TxThreshold;
 364         break;
 365
 366       case Regs::IntrStatus:
 367         reg32 = regs.IntrStatus;
 368         devIntrClear();
 369         break;
 370
 371       case Regs::IntrMask:
 372         reg32 = regs.IntrMask;
 373         break;
 374
 375       case Regs::RxData:
 376         reg64 = regs.RxData;
 377         break;
 378
 379       case Regs::RxDone:
 380       case Regs::RxWait:
 381         reg64 = Regs::set_RxDone_FifoLen(regs.RxDone,
 382                                          min(rxFifo.packets(), 255));
 383         break;
 384
 385       case Regs::TxData:
 386         reg64 = regs.TxData;
 387         break;
 388
 389       case Regs::TxDone:
 390       case Regs::TxWait:
 391         reg64 = Regs::set_TxDone_FifoLen(regs.TxDone,
 392                                          min(txFifo.packets(), 255));
 393         break;
 394
 395       case Regs::HwAddr:
 396         reg64 = params()->eaddr;
 397         break;
 398
 399       default:
 400         panic("reading write only register %s: da=%#x pa=%#x va=%#x size=%d",
 401               Regs::regName(daddr), daddr, req->paddr, req->vaddr, req->size);
 402     }
 403
 404     DPRINTF(EthernetPIO, "read reg=%s done val=%#x\n", Regs::regName(daddr),
 405             Regs::regSize(daddr) == 4 ? reg32 : reg64);
 406
 407     return No_Fault;
 408 }
 409
 410 Fault
 411 Device::write(MemReqPtr &req, const uint8_t *data)
 412 {
 413     assert(config.command & PCI_CMD_MSE);
 414     Addr daddr = req->paddr & 0xfff;
 415
 416     if (Regs::regSize(daddr) == 0)
 417         panic("invalid address: da=%#x pa=%#x va=%#x size=%d",
 418               daddr, req->paddr, req->vaddr, req->size);
 419
 420     if (req->size != Regs::regSize(daddr))
 421         panic("invalid size: reg=%s da=%#x pa=%#x va=%#x size=%d",
 422               Regs::regName(daddr), daddr, req->paddr, req->vaddr, req->size);
 423
 424     uint32_t reg32 = *(uint32_t *)data;
 425     uint64_t reg64 = *(uint64_t *)data;
 426
 427     DPRINTF(EthernetPIO, "write reg=%s val=%#x da=%#x pa=%#x va=%#x size=%d\n",
 428             Regs::regName(daddr), Regs::regSize(daddr) == 4 ? reg32 : reg64,
 429             daddr, req->paddr, req->vaddr, req->size);
 430
 431
 432     switch (daddr) {
 433       case Regs::Config:
 434         changeConfig(reg32);
 435         break;
 436
 437       case Regs::RxThreshold:
 438         regs.RxThreshold = reg32;
 439         break;
 440
 441       case Regs::TxThreshold:
 442         regs.TxThreshold = reg32;
 443         break;
 444
 445       case Regs::IntrMask:
 446         devIntrChangeMask(reg32);
 447         break;
 448
 449       case Regs::RxData:
 450         if (rxState != rxIdle)
 451             panic("receive machine busy with another request!");
 452
 453         regs.RxDone = 0;
 454         regs.RxData = reg64;
 455         if (rxEnable) {
 456             rxState = rxFifoBlock;
 457             rxKick();
 458         }
 459         break;
 460
 461       case Regs::TxData:
 462         if (txState != txIdle)
 463             panic("transmit machine busy with another request!");
 464
 465         regs.TxDone = 0;
 466         regs.TxData = reg64;
 467         if (txEnable) {
 468             txState = txFifoBlock;
 469             txKick();
 470         }
 471         break;
 472
 473       default:
 474         panic("writing read only register %s: da=%#x pa=%#x va=%#x size=%d",
 475               Regs::regName(daddr), daddr, req->paddr, req->vaddr, req->size);
 476     }
 477
 478     return No_Fault;
 479 }
 480
 481 void
 482 Device::devIntrPost(uint32_t interrupts)
 483 {
 484     if ((interrupts & Regs::Intr_Res))
 485         panic("Cannot set a reserved interrupt");
 486
 487     regs.IntrStatus |= interrupts;
 488
 489     DPRINTF(EthernetIntr,
 490             "interrupt written to intStatus: intr=%#x status=%#x mask=%#x\n",
 491             interrupts, regs.IntrStatus, regs.IntrMask);
 492
 493     if ((regs.IntrStatus & regs.IntrMask)) {
 494         Tick when = curTick;
 495         if ((regs.IntrStatus & regs.IntrMask & Regs::Intr_NoDelay) == 0)
 496             when += intrDelay;
 497         cpuIntrPost(when);
 498     }
 499 }
 500
 501 void
 502 Device::devIntrClear(uint32_t interrupts)
 503 {
 504     if ((interrupts & Regs::Intr_Res))
 505         panic("Cannot clear a reserved interrupt");
 506
 507     regs.IntrStatus &= ~interrupts;
 508
 509     DPRINTF(EthernetIntr,
 510             "interrupt cleared from intStatus: intr=%x status=%x mask=%x\n",
 511             interrupts, regs.IntrStatus, regs.IntrMask);
 512
 513     if (!(regs.IntrStatus & regs.IntrMask))
 514         cpuIntrClear();
 515 }
 516
 517 void
 518 Device::devIntrChangeMask(uint32_t newmask)
 519 {
 520     if (regs.IntrMask == newmask)
 521         return;
 522
 523     regs.IntrMask = newmask;
 524
 525     DPRINTF(EthernetIntr,
 526             "interrupt mask changed: intStatus=%x intMask=%x masked=%x\n",
 527             regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
 528
 529     if (regs.IntrStatus & regs.IntrMask)
 530         cpuIntrPost(curTick);
 531     else
 532         cpuIntrClear();
 533 }
 534
 535 void
 536 Base::cpuIntrPost(Tick when)
 537 {
 538     // If the interrupt you want to post is later than an interrupt
 539     // already scheduled, just let it post in the coming one and don't
 540     // schedule another.
 541     // HOWEVER, must be sure that the scheduled intrTick is in the
 542     // future (this was formerly the source of a bug)
 543     /**
 544      * @todo this warning should be removed and the intrTick code should
 545      * be fixed.
 546      */
 547     assert(when >= curTick);
 548     assert(intrTick >= curTick || intrTick == 0);
 549     if (!cpuIntrEnable) {
 550         DPRINTF(EthernetIntr, "interrupts not enabled.\n",
 551                 intrTick);
 552         return;
 553     }
 554
 555     if (when > intrTick && intrTick != 0) {
 556         DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
 557                 intrTick);
 558         return;
 559     }
 560
 561     intrTick = when;
 562     if (intrTick < curTick) {
 563         debug_break();
 564         intrTick = curTick;
 565     }
 566
 567     DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
 568             intrTick);
 569
 570     if (intrEvent)
 571         intrEvent->squash();
 572     intrEvent = new IntrEvent(this, true);
 573     intrEvent->schedule(intrTick);
 574 }
 575
 576 void
 577 Base::cpuInterrupt()
 578 {
 579     assert(intrTick == curTick);
 580
 581     // Whether or not there's a pending interrupt, we don't care about
 582     // it anymore
 583     intrEvent = 0;
 584     intrTick = 0;
 585
 586     // Don't send an interrupt if there's already one
 587     if (cpuPendingIntr) {
 588         DPRINTF(EthernetIntr,
 589                 "would send an interrupt now, but there's already pending\n");
 590     } else {
 591         // Send interrupt
 592         cpuPendingIntr = true;
 593
 594         DPRINTF(EthernetIntr, "posting interrupt\n");
 595         intrPost();
 596     }
 597 }
 598
 599 void
 600 Base::cpuIntrClear()
 601 {
 602     if (!cpuPendingIntr)
 603         return;
 604
 605     if (intrEvent) {
 606         intrEvent->squash();
 607         intrEvent = 0;
 608     }
 609
 610     intrTick = 0;
 611
 612     cpuPendingIntr = false;
 613
 614     DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
 615     intrClear();
 616 }
 617
 618 bool
 619 Base::cpuIntrPending() const
 620 { return cpuPendingIntr; }
 621
 622 void
 623 Device::changeConfig(uint32_t newconf)
 624 {
 625     uint32_t changed = regs.Config ^ newconf;
 626     if (!changed)
 627         return;
 628
 629     regs.Config = newconf;
 630
 631     if ((changed & Regs::Config_Reset)) {
 632         assert(regs.Config & Regs::Config_Reset);
 633         reset();
 634         regs.Config &= ~Regs::Config_Reset;
 635     }
 636
 637     if ((changed & Regs::Config_IntEn)) {
 638         cpuIntrEnable = regs.Config & Regs::Config_IntEn;
 639         if (cpuIntrEnable) {
 640             if (regs.IntrStatus & regs.IntrMask)
 641                 cpuIntrPost(curTick);
 642         } else {
 643             cpuIntrClear();
 644         }
 645     }
 646
 647     if ((changed & Regs::Config_TxEn)) {
 648         txEnable = regs.Config & Regs::Config_TxEn;
 649         if (txEnable)
 650             txKick();
 651     }
 652
 653     if ((changed & Regs::Config_RxEn)) {
 654         rxEnable = regs.Config & Regs::Config_RxEn;
 655         if (rxEnable)
 656             rxKick();
 657     }
 658 }
 659
 660 void
 661 Device::reset()
 662 {
 663     using namespace Regs;
 664     memset(&regs, 0, sizeof(regs));
 665     regs.RxMaxCopy = params()->rx_max_copy;
 666     regs.TxMaxCopy = params()->tx_max_copy;
 667     regs.IntrMask = Intr_TxFifo | Intr_RxFifo | Intr_RxData;
 668
 669     rxState = rxIdle;
 670     txState = txIdle;
 671
 672     rxFifo.clear();
 673     txFifo.clear();
 674 }
 675
 676 void
 677 Device::rxDmaCopy()
 678 {
 679     assert(rxState == rxCopy);
 680     rxState = rxCopyDone;
 681     physmem->dma_write(rxDmaAddr, (uint8_t *)rxDmaData, rxDmaLen);
 682     DPRINTF(EthernetDMA, "rx dma write paddr=%#x len=%d\n",
 683             rxDmaAddr, rxDmaLen);
 684     DDUMP(EthernetDMA, rxDmaData, rxDmaLen);
 685 }
 686
 687 void
 688 Device::rxDmaDone()
 689 {
 690     rxDmaCopy();
 691     rxKick();
 692 }
 693
 694 void
 695 Device::rxKick()
 696 {
 697     DPRINTF(EthernetSM, "receive kick rxState=%s (rxFifo.size=%d)\n",
 698             RxStateStrings[rxState], rxFifo.size());
 699
 700     if (rxKickTick > curTick) {
 701         DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
 702                 rxKickTick);
 703         return;
 704     }
 705
 706   next:
 707     switch (rxState) {
 708       case rxIdle:
 709         if (rxPioRequest) {
 710             pioInterface->respond(rxPioRequest, curTick);
 711             rxPioRequest = 0;
 712         }
 713         goto exit;
 714
 715       case rxFifoBlock:
 716         if (rxPacket) {
 717             rxState = rxBeginCopy;
 718             break;
 719         }
 720
 721         if (rxFifo.empty()) {
 722             DPRINTF(EthernetSM, "receive waiting for data.  Nothing to do.\n");
 723             goto exit;
 724         }
 725
 726         // Grab a new packet from the fifo.
 727         rxPacket = rxFifo.front();
 728         rxPacketBufPtr = rxPacket->data;
 729         rxPktBytes = rxPacket->length;
 730         assert(rxPktBytes);
 731
 732         rxDoneData = 0;
 733         /* scope for variables */ {
 734             IpPtr ip(rxPacket);
 735             if (ip) {
 736                 rxDoneData |= Regs::RxDone_IpPacket;
 737                 rxIpChecksums++;
 738                 if (cksum(ip) != 0) {
 739                     DPRINTF(EthernetCksum, "Rx IP Checksum Error\n");
 740                     rxDoneData |= Regs::RxDone_IpError;
 741                 }
 742                 TcpPtr tcp(ip);
 743                 UdpPtr udp(ip);
 744                 if (tcp) {
 745                     rxDoneData |= Regs::RxDone_TcpPacket;
 746                     rxTcpChecksums++;
 747                     if (cksum(tcp) != 0) {
 748                         DPRINTF(EthernetCksum, "Rx TCP Checksum Error\n");
 749                         rxDoneData |= Regs::RxDone_TcpError;
 750                     }
 751                 } else if (udp) {
 752                     rxDoneData |= Regs::RxDone_UdpPacket;
 753                     rxUdpChecksums++;
 754                     if (cksum(udp) != 0) {
 755                         DPRINTF(EthernetCksum, "Rx UDP Checksum Error\n");
 756                         rxDoneData |= Regs::RxDone_UdpError;
 757                     }
 758                 }
 759             }
 760         }
 761         rxState = rxBeginCopy;
 762         break;
 763
 764       case rxBeginCopy:
 765         rxDmaAddr = plat->pciToDma(Regs::get_RxData_Addr(regs.RxData));
 766         rxDmaLen = min<int>(Regs::get_RxData_Len(regs.RxData), rxPktBytes);
 767         rxDmaData = rxPacketBufPtr;
 768
 769         if (dmaInterface) {
 770             if (!dmaInterface->busy()) {
 771                 dmaInterface->doDMA(WriteInvalidate, rxDmaAddr, rxDmaLen,
 772                                     curTick, &rxDmaEvent, true);
 773                 rxState = rxCopy;
 774             }
 775             goto exit;
 776         }
 777
 778         rxState = rxCopy;
 779         if (dmaWriteDelay != 0 || dmaWriteFactor != 0) {
 780             Tick factor = ((rxDmaLen + ULL(63)) >> ULL(6)) * dmaWriteFactor;
 781             Tick start = curTick + dmaWriteDelay + factor;
 782             rxDmaEvent.schedule(start);
 783             goto exit;
 784         }
 785
 786         rxDmaCopy();
 787         break;
 788
 789       case rxCopy:
 790         DPRINTF(EthernetSM, "receive machine still copying\n");
 791         goto exit;
 792
 793       case rxCopyDone:
 794         regs.RxDone = rxDoneData | rxDmaLen;
 795
 796         if (rxPktBytes == rxDmaLen) {
 797             rxPacket = NULL;
 798             rxFifo.pop();
 799         } else {
 800             regs.RxDone |= Regs::RxDone_More;
 801             rxPktBytes -= rxDmaLen;
 802             rxPacketBufPtr += rxDmaLen;
 803         }
 804
 805         regs.RxDone |= Regs::RxDone_Complete;
 806         devIntrPost(Regs::Intr_RxData);
 807         rxState = rxIdle;
 808         break;
 809
 810       default:
 811         panic("Invalid rxState!");
 812     }
 813
 814     DPRINTF(EthernetSM, "entering next rxState=%s\n",
 815             RxStateStrings[rxState]);
 816
 817     goto next;
 818
 819   exit:
 820     /**
 821      * @todo do we want to schedule a future kick?
 822      */
 823     DPRINTF(EthernetSM, "rx state machine exited rxState=%s\n",
 824             RxStateStrings[rxState]);
 825 }
 826
 827 void
 828 Device::txDmaCopy()
 829 {
 830     assert(txState == txCopy);
 831     txState = txCopyDone;
 832     physmem->dma_read((uint8_t *)txDmaData, txDmaAddr, txDmaLen);
 833     DPRINTF(EthernetDMA, "tx dma read paddr=%#x len=%d\n",
 834             txDmaAddr, txDmaLen);
 835     DDUMP(EthernetDMA, txDmaData, txDmaLen);
 836 }
 837
 838 void
 839 Device::txDmaDone()
 840 {
 841     txDmaCopy();
 842     txKick();
 843 }
 844
 845 void
 846 Device::transmit()
 847 {
 848     if (txFifo.empty()) {
 849         DPRINTF(Ethernet, "nothing to transmit\n");
 850         return;
 851     }
 852
 853     PacketPtr packet = txFifo.front();
 854     if (!interface->sendPacket(packet)) {
 855         DPRINTF(Ethernet, "Packet Transmit: failed txFifo available %d\n",
 856                 txFifo.avail());
 857         goto reschedule;
 858     }
 859
 860     txFifo.pop();
 861
 862 #if TRACING_ON
 863     if (DTRACE(Ethernet)) {
 864         IpPtr ip(packet);
 865         if (ip) {
 866             DPRINTF(Ethernet, "ID is %d\n", ip->id());
 867             TcpPtr tcp(ip);
 868             if (tcp) {
 869                 DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
 870                         tcp->sport(), tcp->dport());
 871             }
 872         }
 873     }
 874 #endif
 875
 876     DDUMP(Ethernet, packet->data, packet->length);
 877     txBytes += packet->length;
 878     txPackets++;
 879
 880     DPRINTF(Ethernet, "Packet Transmit: successful txFifo Available %d\n",
 881             txFifo.avail());
 882
 883     if (txFifo.size() <= params()->tx_fifo_threshold)
 884         devIntrPost(Regs::Intr_TxFifo);
 885
 886     devIntrPost(Regs::Intr_TxDone);
 887
 888   reschedule:
 889    if (!txFifo.empty() && !txEvent.scheduled()) {
 890        DPRINTF(Ethernet, "reschedule transmit\n");
 891        txEvent.schedule(curTick + retryTime);
 892    }
 893 }
 894
 895 void
 896 Device::txKick()
 897 {
 898     DPRINTF(EthernetSM, "transmit kick txState=%s (txFifo.size=%d)\n",
 899             TxStateStrings[txState], txFifo.size());
 900
 901     if (txKickTick > curTick) {
 902         DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
 903                 txKickTick);
 904         return;
 905     }
 906
 907   next:
 908     switch (txState) {
 909       case txIdle:
 910         if (txPioRequest) {
 911             pioInterface->respond(txPioRequest, curTick + pioLatency);
 912             txPioRequest = 0;
 913         }
 914         goto exit;
 915
 916       case txFifoBlock:
 917         if (!txPacket) {
 918             // Grab a new packet from the fifo.
 919             txPacket = new PacketData(16384);
 920             txPacketBufPtr = txPacket->data;
 921         }
 922
 923         if (txFifo.avail() - txPacket->length <
 924             Regs::get_TxData_Len(regs.TxData)) {
 925             DPRINTF(EthernetSM, "transmit fifo full.  Nothing to do.\n");
 926             goto exit;
 927         }
 928
 929         txState = txBeginCopy;
 930         break;
 931
 932       case txBeginCopy:
 933         txDmaAddr = plat->pciToDma(Regs::get_TxData_Addr(regs.TxData));
 934         txDmaLen = Regs::get_TxData_Len(regs.TxData);
 935         txDmaData = txPacketBufPtr;
 936
 937         if (dmaInterface) {
 938             if (!dmaInterface->busy()) {
 939                 dmaInterface->doDMA(Read, txDmaAddr, txDmaLen,
 940                                     curTick, &txDmaEvent, true);
 941                 txState = txCopy;
 942             }
 943
 944             goto exit;
 945         }
 946
 947         txState = txCopy;
 948         if (dmaReadDelay != 0 || dmaReadFactor != 0) {
 949             Tick factor = ((txDmaLen + ULL(63)) >> ULL(6)) * dmaReadFactor;
 950             Tick start = curTick + dmaReadDelay + factor;
 951             txDmaEvent.schedule(start);
 952             goto exit;
 953         }
 954
 955         txDmaCopy();
 956         break;
 957
 958       case txCopy:
 959         DPRINTF(EthernetSM, "transmit machine still copying\n");
 960         goto exit;
 961
 962       case txCopyDone:
 963         txPacket->length += txDmaLen;
 964         if ((regs.TxData & Regs::TxData_More)) {
 965             txPacketBufPtr += txDmaLen;
 966         } else {
 967             assert(txPacket->length <= txFifo.avail());
 968             if ((regs.TxData & Regs::TxData_Checksum)) {
 969                 IpPtr ip(txPacket);
 970                 if (ip) {
 971                     TcpPtr tcp(ip);
 972                     if (tcp) {
 973                         tcp->sum(0);
 974                         tcp->sum(cksum(tcp));
 975                         txTcpChecksums++;
 976                     }
 977
 978                     UdpPtr udp(ip);
 979                     if (udp) {
 980                         udp->sum(0);
 981                         udp->sum(cksum(udp));
 982                         txUdpChecksums++;
 983                     }
 984
 985                     ip->sum(0);
 986                     ip->sum(cksum(ip));
 987                     txIpChecksums++;
 988                 }
 989             }
 990             txFifo.push(txPacket);
 991             txPacket = 0;
 992             transmit();
 993         }
 994
 995         regs.TxDone = txDmaLen | Regs::TxDone_Complete;
 996         devIntrPost(Regs::Intr_TxData);
 997         txState = txIdle;
 998         break;
 999
1000       default:
1001         panic("Invalid txState!");
1002     }
1003
1004     DPRINTF(EthernetSM, "entering next txState=%s\n",
1005             TxStateStrings[txState]);
1006
1007     goto next;
1008
1009   exit:
1010     /**
1011      * @todo do we want to schedule a future kick?
1012      */
1013     DPRINTF(EthernetSM, "tx state machine exited txState=%s\n",
1014             TxStateStrings[txState]);
1015 }
1016
1017 void
1018 Device::transferDone()
1019 {
1020     if (txFifo.empty()) {
1021         DPRINTF(Ethernet, "transfer complete: txFifo empty...nothing to do\n");
1022         return;
1023     }
1024
1025     DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
1026
1027     if (txEvent.scheduled())
1028         txEvent.reschedule(curTick + cycles(1));
1029     else
1030         txEvent.schedule(curTick + cycles(1));
1031 }
1032
1033 bool
1034 Device::rxFilter(const PacketPtr &packet)
1035 {
1036     if (!Regs::get_Config_Filter(regs.Config))
1037         return false;
1038
1039     panic("receive filter not implemented\n");
1040     bool drop = true;
1041
1042 #if 0
1043     string type;
1044
1045     EthHdr *eth = packet->eth();
1046     if (eth->unicast()) {
1047         // If we're accepting all unicast addresses
1048         if (acceptUnicast)
1049             drop = false;
1050
1051         // If we make a perfect match
1052         if (acceptPerfect && params->eaddr == eth.dst())
1053             drop = false;
1054
1055         if (acceptArp && eth->type() == ETH_TYPE_ARP)
1056             drop = false;
1057
1058     } else if (eth->broadcast()) {
1059         // if we're accepting broadcasts
1060         if (acceptBroadcast)
1061             drop = false;
1062
1063     } else if (eth->multicast()) {
1064         // if we're accepting all multicasts
1065         if (acceptMulticast)
1066             drop = false;
1067
1068     }
1069
1070     if (drop) {
1071         DPRINTF(Ethernet, "rxFilter drop\n");
1072         DDUMP(EthernetData, packet->data, packet->length);
1073     }
1074 #endif
1075     return drop;
1076 }
1077
1078 bool
1079 Device::recvPacket(PacketPtr packet)
1080 {
1081     rxBytes += packet->length;
1082     rxPackets++;
1083
1084     DPRINTF(Ethernet, "Receiving packet from wire, rxFifo Available is %d\n",
1085             rxFifo.avail());
1086
1087     if (!rxEnable) {
1088         DPRINTF(Ethernet, "receive disabled...packet dropped\n");
1089         return true;
1090     }
1091
1092     if (rxFilter(packet)) {
1093         DPRINTF(Ethernet, "packet filtered...dropped\n");
1094         return true;
1095     }
1096
1097     if (rxFifo.size() >= params()->rx_fifo_threshold)
1098         devIntrPost(Regs::Intr_RxFifo);
1099
1100     if (!rxFifo.push(packet)) {
1101         DPRINTF(Ethernet,
1102                 "packet will not fit in receive buffer...packet dropped\n");
1103         return false;
1104     }
1105
1106     devIntrPost(Regs::Intr_RxDone);
1107     rxKick();
1108     return true;
1109 }
1110
1111 //=====================================================================
1112 //
1113 //
1114 void
1115 Base::serialize(ostream &os)
1116 {
1117     // Serialize the PciDev base class
1118     PciDev::serialize(os);
1119
1120     SERIALIZE_SCALAR(rxEnable);
1121     SERIALIZE_SCALAR(txEnable);
1122     SERIALIZE_SCALAR(cpuIntrEnable);
1123
1124     /*
1125      * Keep track of pending interrupt status.
1126      */
1127     SERIALIZE_SCALAR(intrTick);
1128     SERIALIZE_SCALAR(cpuPendingIntr);
1129     Tick intrEventTick = 0;
1130     if (intrEvent)
1131         intrEventTick = intrEvent->when();
1132     SERIALIZE_SCALAR(intrEventTick);
1133 }
1134
1135 void
1136 Base::unserialize(Checkpoint *cp, const std::string &section)
1137 {
1138     // Unserialize the PciDev base class
1139     PciDev::unserialize(cp, section);
1140
1141     UNSERIALIZE_SCALAR(rxEnable);
1142     UNSERIALIZE_SCALAR(txEnable);
1143     UNSERIALIZE_SCALAR(cpuIntrEnable);
1144
1145     /*
1146      * Keep track of pending interrupt status.
1147      */
1148     UNSERIALIZE_SCALAR(intrTick);
1149     UNSERIALIZE_SCALAR(cpuPendingIntr);
1150     Tick intrEventTick;
1151     UNSERIALIZE_SCALAR(intrEventTick);
1152     if (intrEventTick) {
1153         intrEvent = new IntrEvent(this, true);
1154         intrEvent->schedule(intrEventTick);
1155     }
1156 }
1157
1158 void
1159 Device::serialize(ostream &os)
1160 {
1161     // Serialize the PciDev base class
1162     Base::serialize(os);
1163
1164     if (rxDmaEvent.scheduled())
1165         rxDmaCopy();
1166
1167     if (txDmaEvent.scheduled())
1168         txDmaCopy();
1169
1170     /*
1171      * Serialize the device registers
1172      */
1173     SERIALIZE_SCALAR(regs.Config);
1174     SERIALIZE_SCALAR(regs.RxMaxCopy);
1175     SERIALIZE_SCALAR(regs.TxMaxCopy);
1176     SERIALIZE_SCALAR(regs.RxThreshold);
1177     SERIALIZE_SCALAR(regs.TxThreshold);
1178     SERIALIZE_SCALAR(regs.IntrStatus);
1179     SERIALIZE_SCALAR(regs.IntrMask);
1180     SERIALIZE_SCALAR(regs.RxData);
1181     SERIALIZE_SCALAR(regs.RxDone);
1182     SERIALIZE_SCALAR(regs.TxData);
1183     SERIALIZE_SCALAR(regs.TxDone);
1184
1185     /*
1186      * Serialize rx state machine
1187      */
1188     int rxState = this->rxState;
1189     SERIALIZE_SCALAR(rxState);
1190     rxFifo.serialize("rxFifo", os);
1191     bool rxPacketExists = rxPacket;
1192     SERIALIZE_SCALAR(rxPacketExists);
1193     if (rxPacketExists) {
1194         rxPacket->serialize("rxPacket", os);
1195         uint32_t rxPktBufPtr = (uint32_t) (rxPacketBufPtr - rxPacket->data);
1196         SERIALIZE_SCALAR(rxPktBufPtr);
1197         SERIALIZE_SCALAR(rxPktBytes);
1198     }
1199     SERIALIZE_SCALAR(rxDoneData);
1200
1201     /*
1202      * Serialize tx state machine
1203      */
1204     int txState = this->txState;
1205     SERIALIZE_SCALAR(txState);
1206     txFifo.serialize("txFifo", os);
1207     bool txPacketExists = txPacket;
1208     SERIALIZE_SCALAR(txPacketExists);
1209     if (txPacketExists) {
1210         txPacket->serialize("txPacket", os);
1211         uint32_t txPktBufPtr = (uint32_t) (txPacketBufPtr - txPacket->data);
1212         SERIALIZE_SCALAR(txPktBufPtr);
1213         SERIALIZE_SCALAR(txPktBytes);
1214     }
1215
1216     /*
1217      * If there's a pending transmit, store the time so we can
1218      * reschedule it later
1219      */
1220     Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
1221     SERIALIZE_SCALAR(transmitTick);
1222 }
1223
1224 void
1225 Device::unserialize(Checkpoint *cp, const std::string &section)
1226 {
1227     // Unserialize the PciDev base class
1228     Base::unserialize(cp, section);
1229
1230     /*
1231      * Unserialize the device registers
1232      */
1233     UNSERIALIZE_SCALAR(regs.Config);
1234     UNSERIALIZE_SCALAR(regs.RxMaxCopy);
1235     UNSERIALIZE_SCALAR(regs.TxMaxCopy);
1236     UNSERIALIZE_SCALAR(regs.RxThreshold);
1237     UNSERIALIZE_SCALAR(regs.TxThreshold);
1238     UNSERIALIZE_SCALAR(regs.IntrStatus);
1239     UNSERIALIZE_SCALAR(regs.IntrMask);
1240     UNSERIALIZE_SCALAR(regs.RxData);
1241     UNSERIALIZE_SCALAR(regs.RxDone);
1242     UNSERIALIZE_SCALAR(regs.TxData);
1243     UNSERIALIZE_SCALAR(regs.TxDone);
1244
1245     /*
1246      * Unserialize rx state machine
1247      */
1248     int rxState;
1249     UNSERIALIZE_SCALAR(rxState);
1250     this->rxState = (RxState) rxState;
1251     rxFifo.unserialize("rxFifo", cp, section);
1252     bool rxPacketExists;
1253     UNSERIALIZE_SCALAR(rxPacketExists);
1254     rxPacket = 0;
1255     if (rxPacketExists) {
1256         rxPacket = new PacketData(16384);
1257         rxPacket->unserialize("rxPacket", cp, section);
1258         uint32_t rxPktBufPtr;
1259         UNSERIALIZE_SCALAR(rxPktBufPtr);
1260         this->rxPacketBufPtr = (uint8_t *) rxPacket->data + rxPktBufPtr;
1261         UNSERIALIZE_SCALAR(rxPktBytes);
1262     }
1263     UNSERIALIZE_SCALAR(rxDoneData);
1264
1265     /*
1266      * Unserialize tx state machine
1267      */
1268     int txState;
1269     UNSERIALIZE_SCALAR(txState);
1270     this->txState = (TxState) txState;
1271     txFifo.unserialize("txFifo", cp, section);
1272     bool txPacketExists;
1273     UNSERIALIZE_SCALAR(txPacketExists);
1274     txPacket = 0;
1275     if (txPacketExists) {
1276         txPacket = new PacketData(16384);
1277         txPacket->unserialize("txPacket", cp, section);
1278         uint32_t txPktBufPtr;
1279         UNSERIALIZE_SCALAR(txPktBufPtr);
1280         this->txPacketBufPtr = (uint8_t *) txPacket->data + txPktBufPtr;
1281         UNSERIALIZE_SCALAR(txPktBytes);
1282     }
1283
1284     /*
1285      * If there's a pending transmit, reschedule it now
1286      */
1287     Tick transmitTick;
1288     UNSERIALIZE_SCALAR(transmitTick);
1289     if (transmitTick)
1290         txEvent.schedule(curTick + transmitTick);
1291
1292     /*
1293      * re-add addrRanges to bus bridges
1294      */
1295     if (pioInterface)
1296         pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
1297 }
1298
1299 Tick
1300 Device::cacheAccess(MemReqPtr &req)
1301 {
1302     //The mask is to give you only the offset into the device register file
1303     Addr daddr = req->paddr - addr;
1304
1305     DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
1306             req->paddr, daddr);
1307
1308     Tick when = curTick + pioLatency;
1309
1310     switch (daddr) {
1311       case Regs::RxDone:
1312         if (rxState != rxIdle) {
1313             rxPioRequest = req;
1314             when = 0;
1315         }
1316         break;
1317
1318       case Regs::TxDone:
1319         if (txState != txIdle) {
1320             txPioRequest = req;
1321             when = 0;
1322         }
1323         break;
1324     }
1325
1326     return when;
1327 }
1328
1329 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Interface)
1330
1331     SimObjectParam<EtherInt *> peer;
1332     SimObjectParam<Device *> device;
1333
1334 END_DECLARE_SIM_OBJECT_PARAMS(Interface)
1335
1336 BEGIN_INIT_SIM_OBJECT_PARAMS(Interface)
1337
1338     INIT_PARAM_DFLT(peer, "peer interface", NULL),
1339     INIT_PARAM(device, "Ethernet device of this interface")
1340
1341 END_INIT_SIM_OBJECT_PARAMS(Interface)
1342
1343 CREATE_SIM_OBJECT(Interface)
1344 {
1345     Interface *dev_int = new Interface(getInstanceName(), device);
1346
1347     EtherInt *p = (EtherInt *)peer;
1348     if (p) {
1349         dev_int->setPeer(p);
1350         p->setPeer(dev_int);
1351     }
1352
1353     return dev_int;
1354 }
1355
1356 REGISTER_SIM_OBJECT("SinicInt", Interface)
1357
1358
1359 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
1360
1361     Param<Tick> clock;
1362
1363     Param<Addr> addr;
1364     SimObjectParam<MemoryController *> mmu;
1365     SimObjectParam<PhysicalMemory *> physmem;
1366     SimObjectParam<PciConfigAll *> configspace;
1367     SimObjectParam<PciConfigData *> configdata;
1368     SimObjectParam<Platform *> platform;
1369     Param<uint32_t> pci_bus;
1370     Param<uint32_t> pci_dev;
1371     Param<uint32_t> pci_func;
1372
1373     SimObjectParam<HierParams *> hier;
1374     SimObjectParam<Bus*> io_bus;
1375     SimObjectParam<Bus*> payload_bus;
1376     Param<Tick> dma_read_delay;
1377     Param<Tick> dma_read_factor;
1378     Param<Tick> dma_write_delay;
1379     Param<Tick> dma_write_factor;
1380     Param<bool> dma_no_allocate;
1381     Param<Tick> pio_latency;
1382     Param<Tick> intr_delay;
1383
1384     Param<Tick> rx_delay;
1385     Param<Tick> tx_delay;
1386     Param<uint32_t> rx_max_copy;
1387     Param<uint32_t> tx_max_copy;
1388     Param<uint32_t> rx_fifo_size;
1389     Param<uint32_t> tx_fifo_size;
1390     Param<uint32_t> rx_fifo_threshold;
1391     Param<uint32_t> tx_fifo_threshold;
1392
1393     Param<bool> rx_filter;
1394     Param<string> hardware_address;
1395
1396 END_DECLARE_SIM_OBJECT_PARAMS(Device)
1397
1398 BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
1399
1400     INIT_PARAM(clock, "State machine cycle time"),
1401
1402     INIT_PARAM(addr, "Device Address"),
1403     INIT_PARAM(mmu, "Memory Controller"),
1404     INIT_PARAM(physmem, "Physical Memory"),
1405     INIT_PARAM(configspace, "PCI Configspace"),
1406     INIT_PARAM(configdata, "PCI Config data"),
1407     INIT_PARAM(platform, "Platform"),
1408     INIT_PARAM(pci_bus, "PCI bus"),
1409     INIT_PARAM(pci_dev, "PCI device number"),
1410     INIT_PARAM(pci_func, "PCI function code"),
1411
1412     INIT_PARAM(hier, "Hierarchy global variables"),
1413     INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
1414     INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
1415     INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
1416     INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
1417     INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
1418     INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
1419     INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
1420     INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
1421     INIT_PARAM(intr_delay, "Interrupt Delay"),
1422
1423     INIT_PARAM(rx_delay, "Receive Delay"),
1424     INIT_PARAM(tx_delay, "Transmit Delay"),
1425     INIT_PARAM(rx_max_copy, "rx max copy"),
1426     INIT_PARAM(tx_max_copy, "rx max copy"),
1427     INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
1428     INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
1429     INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
1430     INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
1431
1432     INIT_PARAM(rx_filter, "Enable Receive Filter"),
1433     INIT_PARAM(hardware_address, "Ethernet Hardware Address")
1434
1435 END_INIT_SIM_OBJECT_PARAMS(Device)
1436
1437
1438 CREATE_SIM_OBJECT(Device)
1439 {
1440     Device::Params *params = new Device::Params;
1441
1442     params->name = getInstanceName();
1443
1444     params->clock = clock;
1445     params->mmu = mmu;
1446     params->physmem = physmem;
1447     params->configSpace = configspace;
1448     params->configData = configdata;
1449     params->plat = platform;
1450     params->busNum = pci_bus;
1451     params->deviceNum = pci_dev;
1452     params->functionNum = pci_func;
1453
1454     params->hier = hier;
1455     params->io_bus = io_bus;
1456     params->payload_bus = payload_bus;
1457     params->dma_read_delay = dma_read_delay;
1458     params->dma_read_factor = dma_read_factor;
1459     params->dma_write_delay = dma_write_delay;
1460     params->dma_write_factor = dma_write_factor;
1461     params->dma_no_allocate = dma_no_allocate;
1462     params->pio_latency = pio_latency;
1463     params->intr_delay = intr_delay;
1464
1465     params->tx_delay = tx_delay;
1466     params->rx_delay = rx_delay;
1467     params->rx_max_copy = rx_max_copy;
1468     params->tx_max_copy = tx_max_copy;
1469     params->rx_fifo_size = rx_fifo_size;
1470     params->tx_fifo_size = tx_fifo_size;
1471     params->rx_fifo_threshold = rx_fifo_threshold;
1472     params->tx_fifo_threshold = tx_fifo_threshold;
1473
1474     params->rx_filter = rx_filter;
1475     params->eaddr = hardware_address;
1476
1477     return new Device(params);
1478 }
1479
1480 REGISTER_SIM_OBJECT("Sinic", Device)
1481
1482 /* namespace Sinic */ }