2 * Copyright (c) 2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef __DEV_SINIC_HH__
30 #define __DEV_SINIC_HH__
32 #include "base/inet.hh"
33 #include "base/statistics.hh"
34 #include "dev/etherint.hh"
35 #include "dev/etherpkt.hh"
36 #include "dev/io_device.hh"
37 #include "dev/pcidev.hh"
38 #include "dev/pktfifo.hh"
39 #include "dev/sinicreg.hh"
40 #include "mem/bus/bus.hh"
41 #include "sim/eventq.hh"
46 class Base : public PciDev
57 void cpuIntrPost(Tick when);
61 typedef EventWrapper<Base, &Base::cpuInterrupt> IntrEvent;
62 friend class IntrEvent;
66 bool cpuIntrPending() const;
67 void cpuIntrAck() { cpuIntrClear(); }
73 virtual void serialize(std::ostream &os);
74 virtual void unserialize(Checkpoint *cp, const std::string §ion);
77 * Construction/Destruction/Parameters
80 struct Params : public PciDev::Params
88 class Device : public Base
92 PhysicalMemory *physmem;
95 /** Receive State Machine States */
104 /** Transmit State Machine states */
113 /** device register file */
118 uint32_t RxThreshold;
119 uint32_t TxThreshold;
130 static const Addr size = Regs::Size;
136 uint8_t *rxPacketBufPtr;
146 uint8_t *txPacketBufPtr;
157 typedef EventWrapper<Device, &Device::rxKick> RxKickEvent;
158 friend class RxKickEvent;
162 typedef EventWrapper<Device, &Device::txKick> TxKickEvent;
163 friend class TxKickEvent;
169 void txEventTransmit()
172 if (txState == txFifoBlock)
175 typedef EventWrapper<Device, &Device::txEventTransmit> TxEvent;
176 friend class TxEvent;
183 * receive address filter
185 bool rxFilter(const PacketPtr &packet);
188 * device configuration
190 void changeConfig(uint32_t newconfig);
193 * device ethernet interface
196 bool recvPacket(PacketPtr packet);
198 void setInterface(Interface *i) { assert(!interface); interface = i; }
206 friend class EventWrapper<Device, &Device::rxDmaDone>;
207 EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
211 friend class EventWrapper<Device, &Device::txDmaDone>;
212 EventWrapper<Device, &Device::rxDmaDone> txDmaEvent;
223 MemReqPtr rxPioRequest;
224 MemReqPtr txPioRequest;
227 * Interrupt management
230 void devIntrPost(uint32_t interrupts);
231 void devIntrClear(uint32_t interrupts = Regs::Intr_All);
232 void devIntrChangeMask(uint32_t newmask);
235 * PCI Configuration interface
238 virtual void WriteConfig(int offset, int size, uint32_t data);
244 virtual Fault read(MemReqPtr &req, uint8_t *data);
245 virtual Fault write(MemReqPtr &req, const uint8_t *data);
246 Tick cacheAccess(MemReqPtr &req);
252 Stats::Scalar<> rxBytes;
253 Stats::Formula rxBandwidth;
254 Stats::Scalar<> rxPackets;
255 Stats::Formula rxPacketRate;
256 Stats::Scalar<> rxIpPackets;
257 Stats::Scalar<> rxTcpPackets;
258 Stats::Scalar<> rxUdpPackets;
259 Stats::Scalar<> rxIpChecksums;
260 Stats::Scalar<> rxTcpChecksums;
261 Stats::Scalar<> rxUdpChecksums;
263 Stats::Scalar<> txBytes;
264 Stats::Formula txBandwidth;
265 Stats::Scalar<> txPackets;
266 Stats::Formula txPacketRate;
267 Stats::Scalar<> txIpPackets;
268 Stats::Scalar<> txTcpPackets;
269 Stats::Scalar<> txUdpPackets;
270 Stats::Scalar<> txIpChecksums;
271 Stats::Scalar<> txTcpChecksums;
272 Stats::Scalar<> txUdpChecksums;
275 virtual void regStats();
278 * Serialization stuff
281 virtual void serialize(std::ostream &os);
282 virtual void unserialize(Checkpoint *cp, const std::string §ion);
285 * Construction/Destruction/Parameters
288 struct Params : public Base::Params
291 PhysicalMemory *pmem;
298 PhysicalMemory *physmem;
299 IntrControl *intctrl;
302 uint32_t rx_max_copy;
303 uint32_t tx_max_copy;
304 uint32_t rx_fifo_size;
305 uint32_t tx_fifo_size;
306 uint32_t rx_fifo_threshold;
307 uint32_t tx_fifo_threshold;
309 Tick dma_read_factor;
310 Tick dma_write_delay;
311 Tick dma_write_factor;
315 const Params *params() const { return (const Params *)_params; }
318 Device(Params *params);
323 * Ethernet Interface for an Ethernet Device
325 class Interface : public EtherInt
331 Interface(const std::string &name, Device *d)
332 : EtherInt(name), dev(d) { dev->setInterface(this); }
334 virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
335 virtual void sendDone() { dev->transferDone(); }
338 /* namespace Sinic */ }
340 #endif // __DEV_SINIC_HH__