Merge zizzer:/z/m5/Bitkeeper/m5
[gem5.git] / dev / tsunami.cc
1 /*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <deque>
30 #include <string>
31 #include <vector>
32
33 #include "cpu/intr_control.hh"
34 #include "dev/simconsole.hh"
35 #include "dev/etherdev.hh"
36 #include "dev/ide_ctrl.hh"
37 #include "dev/tlaser_clock.hh"
38 #include "dev/tsunami_cchip.hh"
39 #include "dev/tsunami_pchip.hh"
40 #include "dev/tsunami_io.hh"
41 #include "dev/tsunami.hh"
42 #include "dev/pciconfigall.hh"
43 #include "sim/builder.hh"
44 #include "sim/system.hh"
45
46 using namespace std;
47
48 Tsunami::Tsunami(const string &name, System *s,
49 IntrControl *ic, PciConfigAll *pci, int intr_freq)
50 : Platform(name, ic, pci, intr_freq), system(s)
51 {
52 // set the back pointer from the system to myself
53 system->platform = this;
54
55 for (int i = 0; i < Tsunami::Max_CPUs; i++)
56 intr_sum_type[i] = 0;
57 }
58
59 Tick
60 Tsunami::intrFrequency()
61 {
62 return io->frequency();
63 }
64
65 void
66 Tsunami::postConsoleInt()
67 {
68 io->postPIC(0x10);
69 }
70
71 void
72 Tsunami::clearConsoleInt()
73 {
74 io->clearPIC(0x10);
75 }
76
77 void
78 Tsunami::postPciInt(int line)
79 {
80 cchip->postDRIR(line);
81 }
82
83 void
84 Tsunami::clearPciInt(int line)
85 {
86 cchip->clearDRIR(line);
87 }
88
89 Addr
90 Tsunami::pciToDma(Addr pciAddr) const
91 {
92 return pchip->translatePciToDma(pciAddr);
93 }
94
95 void
96 Tsunami::serialize(std::ostream &os)
97 {
98 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
99 }
100
101 void
102 Tsunami::unserialize(Checkpoint *cp, const std::string &section)
103 {
104 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
105 }
106
107 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
108
109 SimObjectParam<System *> system;
110 SimObjectParam<SimConsole *> cons;
111 SimObjectParam<IntrControl *> intrctrl;
112 SimObjectParam<PciConfigAll *> pciconfig;
113 Param<int> interrupt_frequency;
114
115 END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
116
117 BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
118
119 INIT_PARAM(system, "system"),
120 INIT_PARAM(cons, "system console"),
121 INIT_PARAM(intrctrl, "interrupt controller"),
122 INIT_PARAM(pciconfig, "PCI configuration"),
123 INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1024)
124
125 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
126
127 CREATE_SIM_OBJECT(Tsunami)
128 {
129 return new Tsunami(getInstanceName(), system, intrctrl, pciconfig,
130 interrupt_frequency);
131 }
132
133 REGISTER_SIM_OBJECT("Tsunami", Tsunami)