Merge zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5
[gem5.git] / dev / tsunami.cc
1 /*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /** @file Implementation of Tsunami platform.
30 */
31
32 #include <deque>
33 #include <string>
34 #include <vector>
35
36 #include "cpu/intr_control.hh"
37 #include "dev/simconsole.hh"
38 #include "dev/ide_ctrl.hh"
39 #include "dev/tsunami_cchip.hh"
40 #include "dev/tsunami_pchip.hh"
41 #include "dev/tsunami_io.hh"
42 #include "dev/tsunami.hh"
43 #include "dev/pciconfigall.hh"
44 #include "sim/builder.hh"
45 #include "sim/system.hh"
46
47 using namespace std;
48
49 Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
50 PciConfigAll *pci)
51 : Platform(name, ic, pci), system(s)
52 {
53 // set the back pointer from the system to myself
54 system->platform = this;
55
56 for (int i = 0; i < Tsunami::Max_CPUs; i++)
57 intr_sum_type[i] = 0;
58 }
59
60 Tick
61 Tsunami::intrFrequency()
62 {
63 return io->frequency();
64 }
65
66 void
67 Tsunami::postConsoleInt()
68 {
69 io->postPIC(0x10);
70 }
71
72 void
73 Tsunami::clearConsoleInt()
74 {
75 io->clearPIC(0x10);
76 }
77
78 void
79 Tsunami::postPciInt(int line)
80 {
81 cchip->postDRIR(line);
82 }
83
84 void
85 Tsunami::clearPciInt(int line)
86 {
87 cchip->clearDRIR(line);
88 }
89
90 Addr
91 Tsunami::pciToDma(Addr pciAddr) const
92 {
93 return pchip->translatePciToDma(pciAddr);
94 }
95
96 void
97 Tsunami::serialize(std::ostream &os)
98 {
99 SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
100 }
101
102 void
103 Tsunami::unserialize(Checkpoint *cp, const std::string &section)
104 {
105 UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
106 }
107
108 BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
109
110 SimObjectParam<System *> system;
111 SimObjectParam<IntrControl *> intrctrl;
112 SimObjectParam<PciConfigAll *> pciconfig;
113
114 END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
115
116 BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
117
118 INIT_PARAM(system, "system"),
119 INIT_PARAM(intrctrl, "interrupt controller"),
120 INIT_PARAM(pciconfig, "PCI configuration")
121
122 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
123
124 CREATE_SIM_OBJECT(Tsunami)
125 {
126 return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
127 }
128
129 REGISTER_SIM_OBJECT("Tsunami", Tsunami)